📄 clock.map.rpt
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; Total logic cells in carry chains ; 4 ;
; I/O pins ; 19 ;
; Maximum fan-out node ; RST ;
; Maximum fan-out ; 24 ;
; Total fan-out ; 353 ;
; Average fan-out ; 3.36 ;
+-----------------------------------+---------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+---------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+---------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------------------------------------------+--------------+
; |clock ; 86 (0) ; 27 ; 0 ; 19 ; 59 (0) ; 2 (0) ; 25 (0) ; 4 (0) ; 0 (0) ; |clock ; work ;
; |CNT12_24:U2| ; 32 (28) ; 8 ; 0 ; 0 ; 24 (20) ; 2 (2) ; 6 (6) ; 4 (0) ; 0 (0) ; |clock|CNT12_24:U2 ; work ;
; |lpm_add_sub:Add0| ; 4 (0) ; 0 ; 0 ; 0 ; 4 (0) ; 0 (0) ; 0 (0) ; 4 (0) ; 0 (0) ; |clock|CNT12_24:U2|lpm_add_sub:Add0 ; work ;
; |addcore:adder| ; 4 (1) ; 0 ; 0 ; 0 ; 4 (1) ; 0 (0) ; 0 (0) ; 4 (1) ; 0 (0) ; |clock|CNT12_24:U2|lpm_add_sub:Add0|addcore:adder ; work ;
; |a_csnbuffer:result_node| ; 3 (3) ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 0 (0) ; 3 (3) ; 0 (0) ; |clock|CNT12_24:U2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node ; work ;
; |CNT60:U3| ; 12 (12) ; 8 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 8 (8) ; 0 (0) ; 0 (0) ; |clock|CNT60:U3 ; work ;
; |CNT60:U4| ; 12 (12) ; 8 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 8 (8) ; 0 (0) ; 0 (0) ; |clock|CNT60:U4 ; work ;
; |CONTROL:U1| ; 2 (2) ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |clock|CONTROL:U1 ; work ;
; |LED:U5| ; 28 (28) ; 3 ; 0 ; 0 ; 25 (25) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |clock|LED:U5 ; work ;
+---------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 27 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 24 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 11 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------------------------------------------+
; Source assignments for CNT12_24:U2|lpm_add_sub:Add0|addcore:adder ;
+---------------------------+-------+------+------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------+-------+------+------------------------+
; SUPPRESS_DA_RULE_INTERNAL ; A103 ; - ; - ;
+---------------------------+-------+------+------------------------+
+-------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: CNT12_24:U2|lpm_add_sub:Add0 ;
+------------------------+-------------+----------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+----------------------------------------+
; LPM_WIDTH ; 4 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; NO ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 1 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; FLEX10K ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_njh ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 8.0 Build 215 05/29/2008 SJ Web Edition
Info: Processing started: Thu Dec 04 16:54:34 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock
Info: Found 2 design units, including 1 entities, in source file clock.vhd
Info: Found design unit 1: clock-one
Info: Found entity 1: clock
Info: Found 2 design units, including 1 entities, in source file cnt12_24.vhd
Info: Found design unit 1: CNT12_24-one
Info: Found entity 1: CNT12_24
Info: Found 2 design units, including 1 entities, in source file cnt60.vhd
Info: Found design unit 1: CNT60-one
Info: Found entity 1: CNT60
Info: Found 2 design units, including 1 entities, in source file control.vhd
Info: Found design unit 1: CONTROL-one
Info: Found entity 1: CONTROL
Info: Found 2 design units, including 1 entities, in source file timer.vhd
Info: Found design unit 1: FM-one
Info: Found entity 1: FM
Info: Found 2 design units, including 1 entities, in source file led.vhd
Info: Found design unit 1: LED-one
Info: Found entity 1: LED
Info: Elaborating entity "clock" for the top level hierarchy
Warning (10541): VHDL Signal Declaration warning at clock.vhd(49): used implicit default value for signal "MFS" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
Warning (10541): VHDL Signal Declaration warning at clock.vhd(49): used implicit default value for signal "MFG" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
Warning (10541): VHDL Signal Declaration warning at clock.vhd(49): used implicit default value for signal "SFS" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
Warning (10541): VHDL Signal Declaration warning at clock.vhd(49): used implicit default value for signal "SFG" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
Info: Elaborating entity "CONTROL" for hierarchy "CONTROL:U1"
Warning (10492): VHDL Process Statement warning at control.vhd(15): signal "QM" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at control.vhd(16): signal "QS" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at control.vhd(11): inferring latch(es) for signal or variable "ENH", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at control.vhd(11): inferring latch(es) for signal or variable "ENM", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at control.vhd(11): inferring latch(es) for signal or variable "CPH", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at control.vhd(11): inferring latch(es) for signal or variable "CPM", which holds its previous value in one or more paths through the process
Info: Elaborating entity "CNT12_24" for hierarchy "CNT12_24:U2"
Info: Elaborating entity "CNT60" for hierarchy "CNT60:U3"
Info: Elaborating entity "LED" for hierarchy "LED:U5"
Info: Elaborating entity "FM" for hierarchy "FM:U6"
Warning (10631): VHDL Process Statement warning at timer.vhd(15): inferring latch(es) for signal or variable "QFM", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "QFM" at timer.vhd(15)
Warning: LATCH primitive "FM:U6|QFM" is permanently disabled
Info: Inferred 1 megafunctions from design logic
Info: Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "CNT12_24:U2|Add0"
Info: Elaborated megafunction instantiation "CNT12_24:U2|lpm_add_sub:Add0"
Info: Instantiated megafunction "CNT12_24:U2|lpm_add_sub:Add0" with the following parameter:
Info: Parameter "LPM_WIDTH" = "4"
Info: Parameter "LPM_DIRECTION" = "ADD"
Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
Info: Parameter "ONE_INPUT_IS_CONSTANT" = "NO"
Info: Elaborated megafunction instantiation "CNT12_24:U2|lpm_add_sub:Add0|addcore:adder", which is child of megafunction instantiation "CNT12_24:U2|lpm_add_sub:Add0"
Info: Elaborated megafunction instantiation "CNT12_24:U2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:oflow_node", which is child of megafunction instantiation "CNT12_24:U2|lpm_add_sub:Add0"
Info: Elaborated megafunction instantiation "CNT12_24:U2|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node", which is child of megafunction instantiation "CNT12_24:U2|lpm_add_sub:Add0"
Info: Elaborated megafunction instantiation "CNT12_24:U2|lpm_add_sub:Add0|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "CNT12_24:U2|lpm_add_sub:Add0"
Info: Elaborated megafunction instantiation "CNT12_24:U2|lpm_add_sub:Add0|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "CNT12_24:U2|lpm_add_sub:Add0"
Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "FeM" is stuck at GND
Warning: Design contains 1 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "CLK2048"
Info: Implemented 105 device resources after synthesis - the final resource count might be different
Info: Implemented 8 input pins
Info: Implemented 11 output pins
Info: Implemented 86 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 16 warnings
Info: Peak virtual memory: 174 megabytes
Info: Processing ended: Thu Dec 04 16:54:40 2008
Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:05
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