led_run_test.tan.qmsg

走马灯设计

{ "Info" "ITDB_TSU_RESULT" "led\[0\]~reg0 rst_n mclk 0.492 ns register " "Info: tsu for register \"led\[0\]~reg0\" (data pin = \"rst_n\", clock pin = \"mclk\") is 0.492 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.409 ns + Longest pin register " "Info: + Longest pin to register delay is 3.409 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rst_n 1 PIN PIN_131 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_131; Fanout = 6; PIN Node = 'rst_n'" {  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "" { rst_n } "NODE_NAME" } "" } } { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.867 ns) 3.409 ns led\[0\]~reg0 2 REG LC_X1_Y17_N8 1 " "Info: 2: + IC(1.073 ns) + CELL(0.867 ns) = 3.409 ns; Loc. = LC_X1_Y17_N8; Fanout = 1; REG Node = 'led\[0\]~reg0'" {  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "1.940 ns" { rst_n led[0]~reg0 } "NODE_NAME" } "" } } { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns 68.52 % " "Info: Total cell delay = 2.336 ns ( 68.52 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.073 ns 31.48 % " "Info: Total interconnect delay = 1.073 ns ( 31.48 % )" {  } {  } 0}  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "3.409 ns" { rst_n led[0]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.409 ns" { rst_n rst_n~out0 led[0]~reg0 } { 0.000ns 0.000ns 1.073ns } { 0.000ns 1.469ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 22 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk destination 2.954 ns - Shortest register " "Info: - Shortest clock path from clock \"mclk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mclk 1 CLK PIN_153 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 6; CLK Node = 'mclk'" {  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "" { mclk } "NODE_NAME" } "" } } { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns led\[0\]~reg0 2 REG LC_X1_Y17_N8 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y17_N8; Fanout = 1; REG Node = 'led\[0\]~reg0'" {  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "1.485 ns" { mclk led[0]~reg0 } "NODE_NAME" } "" } } { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "2.954 ns" { mclk led[0]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { mclk mclk~out0 led[0]~reg0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "3.409 ns" { rst_n led[0]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.409 ns" { rst_n rst_n~out0 led[0]~reg0 } { 0.000ns 0.000ns 1.073ns } { 0.000ns 1.469ns 0.867ns } } } { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "2.954 ns" { mclk led[0]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { mclk mclk~out0 led[0]~reg0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "mclk led\[1\] led\[1\]~reg0 6.890 ns register " "Info: tco from clock \"mclk\" to destination pin \"led\[1\]\" through register \"led\[1\]~reg0\" is 6.890 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk source 2.954 ns + Longest register " "Info: + Longest clock path from clock \"mclk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mclk 1 CLK PIN_153 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 6; CLK Node = 'mclk'" {  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "" { mclk } "NODE_NAME" } "" } } { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns led\[1\]~reg0 2 REG LC_X1_Y17_N4 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y17_N4; Fanout = 1; REG Node = 'led\[1\]~reg0'" {  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "1.485 ns" { mclk led[1]~reg0 } "NODE_NAME" } "" } } { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "2.954 ns" { mclk led[1]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { mclk mclk~out0 led[1]~reg0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 22 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.712 ns + Longest register pin " "Info: + Longest register to pin delay is 3.712 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led\[1\]~reg0 1 REG LC_X1_Y17_N4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y17_N4; Fanout = 1; REG Node = 'led\[1\]~reg0'" {  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "" { led[1]~reg0 } "NODE_NAME" } "" } } { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.588 ns) + CELL(2.124 ns) 3.712 ns led\[1\] 2 PIN PIN_8 0 " "Info: 2: + IC(1.588 ns) + CELL(2.124 ns) = 3.712 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'led\[1\]'" {  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "3.712 ns" { led[1]~reg0 led[1] } "NODE_NAME" } "" } } { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 57.22 % " "Info: Total cell delay = 2.124 ns ( 57.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.588 ns 42.78 % " "Info: Total interconnect delay = 1.588 ns ( 42.78 % )" {  } {  } 0}  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "3.712 ns" { led[1]~reg0 led[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.712 ns" { led[1]~reg0 led[1] } { 0.000ns 1.588ns } { 0.000ns 2.124ns } } }  } 0}  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "2.954 ns" { mclk led[1]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { mclk mclk~out0 led[1]~reg0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "3.712 ns" { led[1]~reg0 led[1] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.712 ns" { led[1]~reg0 led[1] } { 0.000ns 1.588ns } { 0.000ns 2.124ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "led\[0\]~reg0 rst_n mclk -0.440 ns register " "Info: th for register \"led\[0\]~reg0\" (data pin = \"rst_n\", clock pin = \"mclk\") is -0.440 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk destination 2.954 ns + Longest register " "Info: + Longest clock path from clock \"mclk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns mclk 1 CLK PIN_153 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 6; CLK Node = 'mclk'" {  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "" { mclk } "NODE_NAME" } "" } } { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns led\[0\]~reg0 2 REG LC_X1_Y17_N8 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y17_N8; Fanout = 1; REG Node = 'led\[0\]~reg0'" {  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "1.485 ns" { mclk led[0]~reg0 } "NODE_NAME" } "" } } { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "2.954 ns" { mclk led[0]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { mclk mclk~out0 led[0]~reg0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 22 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.409 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.409 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rst_n 1 PIN PIN_131 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_131; Fanout = 6; PIN Node = 'rst_n'" {  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "" { rst_n } "NODE_NAME" } "" } } { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.867 ns) 3.409 ns led\[0\]~reg0 2 REG LC_X1_Y17_N8 1 " "Info: 2: + IC(1.073 ns) + CELL(0.867 ns) = 3.409 ns; Loc. = LC_X1_Y17_N8; Fanout = 1; REG Node = 'led\[0\]~reg0'" {  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "1.940 ns" { rst_n led[0]~reg0 } "NODE_NAME" } "" } } { "led_run.v" "" { Text "F:/altera/led_run/led_run.v" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns 68.52 % " "Info: Total cell delay = 2.336 ns ( 68.52 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.073 ns 31.48 % " "Info: Total interconnect delay = 1.073 ns ( 31.48 % )" {  } {  } 0}  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "3.409 ns" { rst_n led[0]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.409 ns" { rst_n rst_n~out0 led[0]~reg0 } { 0.000ns 0.000ns 1.073ns } { 0.000ns 1.469ns 0.867ns } } }  } 0}  } { { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "2.954 ns" { mclk led[0]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { mclk mclk~out0 led[0]~reg0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/altera/led_run/db/led_run_test_cmp.qrpt" "" { Report "F:/altera/led_run/db/led_run_test_cmp.qrpt" Compiler "led_run_test" "UNKNOWN" "V1" "F:/altera/led_run/db/led_run.quartus_db" { Floorplan "F:/altera/led_run/" "" "3.409 ns" { rst_n led[0]~reg0 } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "3.409 ns" { rst_n rst_n~out0 led[0]~reg0 } { 0.000ns 0.000ns 1.073ns } { 0.000ns 1.469ns 0.867ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 13 20:49:50 2009 " "Info: Processing ended: Wed May 13 20:49:50 2009" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}