miller.tan.qmsg

使用VHDL实现基带码中密勒码的编解码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register sav2\[1\] encodeout\[0\]~reg0 420.17 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 420.17 MHz between source register \"sav2\[1\]\" and destination register \"encodeout\[0\]~reg0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.619 ns + Longest register register " "Info: + Longest register to register delay is 1.619 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sav2\[1\] 1 REG LCFF_X1_Y5_N15 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y5_N15; Fanout = 6; REG Node = 'sav2\[1\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { sav2[1] } "NODE_NAME" } } { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.315 ns) + CELL(0.419 ns) 0.734 ns encodeout\[0\]~488 2 COMB LCCOMB_X1_Y5_N28 3 " "Info: 2: + IC(0.315 ns) + CELL(0.419 ns) = 0.734 ns; Loc. = LCCOMB_X1_Y5_N28; Fanout = 3; COMB Node = 'encodeout\[0\]~488'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.734 ns" { sav2[1] encodeout[0]~488 } "NODE_NAME" } } { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.225 ns) + CELL(0.660 ns) 1.619 ns encodeout\[0\]~reg0 3 REG LCFF_X1_Y5_N25 1 " "Info: 3: + IC(0.225 ns) + CELL(0.660 ns) = 1.619 ns; Loc. = LCFF_X1_Y5_N25; Fanout = 1; REG Node = 'encodeout\[0\]~reg0'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.885 ns" { encodeout[0]~488 encodeout[0]~reg0 } "NODE_NAME" } } { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 22 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.079 ns ( 66.65 % ) " "Info: Total cell delay = 1.079 ns ( 66.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.540 ns ( 33.35 % ) " "Info: Total interconnect delay = 0.540 ns ( 33.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.619 ns" { sav2[1] encodeout[0]~488 encodeout[0]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.619 ns" { sav2[1] {} encodeout[0]~488 {} encodeout[0]~reg0 {} } { 0.000ns 0.315ns 0.225ns } { 0.000ns 0.419ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.345 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.345 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 6 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.697 ns) + CELL(0.537 ns) 2.345 ns encodeout\[0\]~reg0 3 REG LCFF_X1_Y5_N25 1 " "Info: 3: + IC(0.697 ns) + CELL(0.537 ns) = 2.345 ns; Loc. = LCFF_X1_Y5_N25; Fanout = 1; REG Node = 'encodeout\[0\]~reg0'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.234 ns" { clk~clkctrl encodeout[0]~reg0 } "NODE_NAME" } } { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 22 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 65.07 % ) " "Info: Total cell delay = 1.526 ns ( 65.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.819 ns ( 34.93 % ) " "Info: Total interconnect delay = 0.819 ns ( 34.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.345 ns" { clk clk~clkctrl encodeout[0]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.345 ns" { clk {} clk~combout {} clk~clkctrl {} encodeout[0]~reg0 {} } { 0.000ns 0.000ns 0.122ns 0.697ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.345 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.345 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 6 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.697 ns) + CELL(0.537 ns) 2.345 ns sav2\[1\] 3 REG LCFF_X1_Y5_N15 6 " "Info: 3: + IC(0.697 ns) + CELL(0.537 ns) = 2.345 ns; Loc. = LCFF_X1_Y5_N15; Fanout = 6; REG Node = 'sav2\[1\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.234 ns" { clk~clkctrl sav2[1] } "NODE_NAME" } } { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 65.07 % ) " "Info: Total cell delay = 1.526 ns ( 65.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.819 ns ( 34.93 % ) " "Info: Total interconnect delay = 0.819 ns ( 34.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.345 ns" { clk clk~clkctrl sav2[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.345 ns" { clk {} clk~combout {} clk~clkctrl {} sav2[1] {} } { 0.000ns 0.000ns 0.122ns 0.697ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.345 ns" { clk clk~clkctrl encodeout[0]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.345 ns" { clk {} clk~combout {} clk~clkctrl {} encodeout[0]~reg0 {} } { 0.000ns 0.000ns 0.122ns 0.697ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.345 ns" { clk clk~clkctrl sav2[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.345 ns" { clk {} clk~combout {} clk~clkctrl {} sav2[1] {} } { 0.000ns 0.000ns 0.122ns 0.697ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 22 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.619 ns" { sav2[1] encodeout[0]~488 encodeout[0]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.619 ns" { sav2[1] {} encodeout[0]~488 {} encodeout[0]~reg0 {} } { 0.000ns 0.315ns 0.225ns } { 0.000ns 0.419ns 0.660ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.345 ns" { clk clk~clkctrl encodeout[0]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.345 ns" { clk {} clk~combout {} clk~clkctrl {} encodeout[0]~reg0 {} } { 0.000ns 0.000ns 0.122ns 0.697ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.345 ns" { clk clk~clkctrl sav2[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.345 ns" { clk {} clk~combout {} clk~clkctrl {} sav2[1] {} } { 0.000ns 0.000ns 0.122ns 0.697ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { encodeout[0]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { encodeout[0]~reg0 {} } {  } {  } "" } } { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 22 0 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "sav2\[0\] en clk 4.641 ns register " "Info: tsu for register \"sav2\[0\]\" (data pin = \"en\", clock pin = \"clk\") is 4.641 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.022 ns + Longest pin register " "Info: + Longest pin to register delay is 7.022 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.850 ns) 0.850 ns en 1 PIN PIN_60 4 " "Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_60; Fanout = 4; PIN Node = 'en'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.512 ns) + CELL(0.660 ns) 7.022 ns sav2\[0\] 2 REG LCFF_X1_Y5_N19 6 " "Info: 2: + IC(5.512 ns) + CELL(0.660 ns) = 7.022 ns; Loc. = LCFF_X1_Y5_N19; Fanout = 6; REG Node = 'sav2\[0\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.172 ns" { en sav2[0] } "NODE_NAME" } } { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.510 ns ( 21.50 % ) " "Info: Total cell delay = 1.510 ns ( 21.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.512 ns ( 78.50 % ) " "Info: Total interconnect delay = 5.512 ns ( 78.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.022 ns" { en sav2[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.022 ns" { en {} en~combout {} sav2[0] {} } { 0.000ns 0.000ns 5.512ns } { 0.000ns 0.850ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.345 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.345 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 6 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.697 ns) + CELL(0.537 ns) 2.345 ns sav2\[0\] 3 REG LCFF_X1_Y5_N19 6 " "Info: 3: + IC(0.697 ns) + CELL(0.537 ns) = 2.345 ns; Loc. = LCFF_X1_Y5_N19; Fanout = 6; REG Node = 'sav2\[0\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.234 ns" { clk~clkctrl sav2[0] } "NODE_NAME" } } { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 65.07 % ) " "Info: Total cell delay = 1.526 ns ( 65.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.819 ns ( 34.93 % ) " "Info: Total interconnect delay = 0.819 ns ( 34.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.345 ns" { clk clk~clkctrl sav2[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.345 ns" { clk {} clk~combout {} clk~clkctrl {} sav2[0] {} } { 0.000ns 0.000ns 0.122ns 0.697ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.022 ns" { en sav2[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.022 ns" { en {} en~combout {} sav2[0] {} } { 0.000ns 0.000ns 5.512ns } { 0.000ns 0.850ns 0.660ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.345 ns" { clk clk~clkctrl sav2[0] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.345 ns" { clk {} clk~combout {} clk~clkctrl {} sav2[0] {} } { 0.000ns 0.000ns 0.122ns 0.697ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk encodeout\[1\] encodeout\[1\]~reg0 5.761 ns register " "Info: tco from clock \"clk\" to destination pin \"encodeout\[1\]\" through register \"encodeout\[1\]~reg0\" is 5.761 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.345 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.345 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 6 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.697 ns) + CELL(0.537 ns) 2.345 ns encodeout\[1\]~reg0 3 REG LCFF_X1_Y5_N21 1 " "Info: 3: + IC(0.697 ns) + CELL(0.537 ns) = 2.345 ns; Loc. = LCFF_X1_Y5_N21; Fanout = 1; REG Node = 'encodeout\[1\]~reg0'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.234 ns" { clk~clkctrl encodeout[1]~reg0 } "NODE_NAME" } } { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 22 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 65.07 % ) " "Info: Total cell delay = 1.526 ns ( 65.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.819 ns ( 34.93 % ) " "Info: Total interconnect delay = 0.819 ns ( 34.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.345 ns" { clk clk~clkctrl encodeout[1]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.345 ns" { clk {} clk~combout {} clk~clkctrl {} encodeout[1]~reg0 {} } { 0.000ns 0.000ns 0.122ns 0.697ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 22 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.166 ns + Longest register pin " "Info: + Longest register to pin delay is 3.166 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns encodeout\[1\]~reg0 1 REG LCFF_X1_Y5_N21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y5_N21; Fanout = 1; REG Node = 'encodeout\[1\]~reg0'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { encodeout[1]~reg0 } "NODE_NAME" } } { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 22 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.514 ns) + CELL(2.652 ns) 3.166 ns encodeout\[1\] 2 PIN PIN_27 0 " "Info: 2: + IC(0.514 ns) + CELL(2.652 ns) = 3.166 ns; Loc. = PIN_27; Fanout = 0; PIN Node = 'encodeout\[1\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.166 ns" { encodeout[1]~reg0 encodeout[1] } "NODE_NAME" } } { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.652 ns ( 83.77 % ) " "Info: Total cell delay = 2.652 ns ( 83.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.514 ns ( 16.23 % ) " "Info: Total interconnect delay = 0.514 ns ( 16.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.166 ns" { encodeout[1]~reg0 encodeout[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.166 ns" { encodeout[1]~reg0 {} encodeout[1] {} } { 0.000ns 0.514ns } { 0.000ns 2.652ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.345 ns" { clk clk~clkctrl encodeout[1]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.345 ns" { clk {} clk~combout {} clk~clkctrl {} encodeout[1]~reg0 {} } { 0.000ns 0.000ns 0.122ns 0.697ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.166 ns" { encodeout[1]~reg0 encodeout[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.166 ns" { encodeout[1]~reg0 {} encodeout[1] {} } { 0.000ns 0.514ns } { 0.000ns 2.652ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "encodeout\[0\]~reg0 datain clk -4.054 ns register " "Info: th for register \"encodeout\[0\]~reg0\" (data pin = \"datain\", clock pin = \"clk\") is -4.054 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.345 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.345 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 6 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 6; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.697 ns) + CELL(0.537 ns) 2.345 ns encodeout\[0\]~reg0 3 REG LCFF_X1_Y5_N25 1 " "Info: 3: + IC(0.697 ns) + CELL(0.537 ns) = 2.345 ns; Loc. = LCFF_X1_Y5_N25; Fanout = 1; REG Node = 'encodeout\[0\]~reg0'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.234 ns" { clk~clkctrl encodeout[0]~reg0 } "NODE_NAME" } } { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 22 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 65.07 % ) " "Info: Total cell delay = 1.526 ns ( 65.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.819 ns ( 34.93 % ) " "Info: Total interconnect delay = 0.819 ns ( 34.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.345 ns" { clk clk~clkctrl encodeout[0]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.345 ns" { clk {} clk~combout {} clk~clkctrl {} encodeout[0]~reg0 {} } { 0.000ns 0.000ns 0.122ns 0.697ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 22 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.665 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.665 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.850 ns) 0.850 ns datain 1 PIN PIN_52 5 " "Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_52; Fanout = 5; PIN Node = 'datain'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { datain } "NODE_NAME" } } { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.456 ns) + CELL(0.275 ns) 6.581 ns encodeout\[0\]~487 2 COMB LCCOMB_X1_Y5_N24 1 " "Info: 2: + IC(5.456 ns) + CELL(0.275 ns) = 6.581 ns; Loc. = LCCOMB_X1_Y5_N24; Fanout = 1; COMB Node = 'encodeout\[0\]~487'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.731 ns" { datain encodeout[0]~487 } "NODE_NAME" } } { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.665 ns encodeout\[0\]~reg0 3 REG LCFF_X1_Y5_N25 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.665 ns; Loc. = LCFF_X1_Y5_N25; Fanout = 1; REG Node = 'encodeout\[0\]~reg0'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { encodeout[0]~487 encodeout[0]~reg0 } "NODE_NAME" } } { "miller_encoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_encoder.vhd" 22 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.209 ns ( 18.14 % ) " "Info: Total cell delay = 1.209 ns ( 18.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.456 ns ( 81.86 % ) " "Info: Total interconnect delay = 5.456 ns ( 81.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.665 ns" { datain encodeout[0]~487 encodeout[0]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.665 ns" { datain {} datain~combout {} encodeout[0]~487 {} encodeout[0]~reg0 {} } { 0.000ns 0.000ns 5.456ns 0.000ns } { 0.000ns 0.850ns 0.275ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.345 ns" { clk clk~clkctrl encodeout[0]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.345 ns" { clk {} clk~combout {} clk~clkctrl {} encodeout[0]~reg0 {} } { 0.000ns 0.000ns 0.122ns 0.697ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.665 ns" { datain encodeout[0]~487 encodeout[0]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.665 ns" { datain {} datain~combout {} encodeout[0]~487 {} encodeout[0]~reg0 {} } { 0.000ns 0.000ns 5.456ns 0.000ns } { 0.000ns 0.850ns 0.275ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}