prev_cmp_miller.tan.qmsg

使用VHDL实现基带码中密勒码的编解码

{ "Info" "ITDB_TSU_RESULT" "decodeout~reg0 encodein\[1\] clk 4.248 ns register " "Info: tsu for register \"decodeout~reg0\" (data pin = \"encodein\[1\]\", clock pin = \"clk\") is 4.248 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.629 ns + Longest pin register " "Info: + Longest pin to register delay is 6.629 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.850 ns) 0.850 ns encodein\[1\] 1 PIN PIN_52 1 " "Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_52; Fanout = 1; PIN Node = 'encodein\[1\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { encodein[1] } "NODE_NAME" } } { "miller_decoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_decoder.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.420 ns) + CELL(0.275 ns) 6.545 ns process0~4 2 COMB LCCOMB_X1_Y5_N24 1 " "Info: 2: + IC(5.420 ns) + CELL(0.275 ns) = 6.545 ns; Loc. = LCCOMB_X1_Y5_N24; Fanout = 1; COMB Node = 'process0~4'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.695 ns" { encodein[1] process0~4 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.629 ns decodeout~reg0 3 REG LCFF_X1_Y5_N25 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.629 ns; Loc. = LCFF_X1_Y5_N25; Fanout = 1; REG Node = 'decodeout~reg0'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { process0~4 decodeout~reg0 } "NODE_NAME" } } { "miller_decoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_decoder.vhd" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.209 ns ( 18.24 % ) " "Info: Total cell delay = 1.209 ns ( 18.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.420 ns ( 81.76 % ) " "Info: Total interconnect delay = 5.420 ns ( 81.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.629 ns" { encodein[1] process0~4 decodeout~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.629 ns" { encodein[1] {} encodein[1]~combout {} process0~4 {} decodeout~reg0 {} } { 0.000ns 0.000ns 5.420ns 0.000ns } { 0.000ns 0.850ns 0.275ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "miller_decoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_decoder.vhd" 20 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.345 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.345 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "miller_decoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_decoder.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 2 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "miller_decoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_decoder.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.697 ns) + CELL(0.537 ns) 2.345 ns decodeout~reg0 3 REG LCFF_X1_Y5_N25 1 " "Info: 3: + IC(0.697 ns) + CELL(0.537 ns) = 2.345 ns; Loc. = LCFF_X1_Y5_N25; Fanout = 1; REG Node = 'decodeout~reg0'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.234 ns" { clk~clkctrl decodeout~reg0 } "NODE_NAME" } } { "miller_decoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_decoder.vhd" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 65.07 % ) " "Info: Total cell delay = 1.526 ns ( 65.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.819 ns ( 34.93 % ) " "Info: Total interconnect delay = 0.819 ns ( 34.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.345 ns" { clk clk~clkctrl decodeout~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.345 ns" { clk {} clk~combout {} clk~clkctrl {} decodeout~reg0 {} } { 0.000ns 0.000ns 0.122ns 0.697ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.629 ns" { encodein[1] process0~4 decodeout~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.629 ns" { encodein[1] {} encodein[1]~combout {} process0~4 {} decodeout~reg0 {} } { 0.000ns 0.000ns 5.420ns 0.000ns } { 0.000ns 0.850ns 0.275ns 0.084ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.345 ns" { clk clk~clkctrl decodeout~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.345 ns" { clk {} clk~combout {} clk~clkctrl {} decodeout~reg0 {} } { 0.000ns 0.000ns 0.122ns 0.697ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk decodeout decodeout~reg0 5.752 ns register " "Info: tco from clock \"clk\" to destination pin \"decodeout\" through register \"decodeout~reg0\" is 5.752 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.345 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.345 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "miller_decoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_decoder.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 2 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "miller_decoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_decoder.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.697 ns) + CELL(0.537 ns) 2.345 ns decodeout~reg0 3 REG LCFF_X1_Y5_N25 1 " "Info: 3: + IC(0.697 ns) + CELL(0.537 ns) = 2.345 ns; Loc. = LCFF_X1_Y5_N25; Fanout = 1; REG Node = 'decodeout~reg0'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.234 ns" { clk~clkctrl decodeout~reg0 } "NODE_NAME" } } { "miller_decoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_decoder.vhd" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 65.07 % ) " "Info: Total cell delay = 1.526 ns ( 65.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.819 ns ( 34.93 % ) " "Info: Total interconnect delay = 0.819 ns ( 34.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.345 ns" { clk clk~clkctrl decodeout~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.345 ns" { clk {} clk~combout {} clk~clkctrl {} decodeout~reg0 {} } { 0.000ns 0.000ns 0.122ns 0.697ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "miller_decoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_decoder.vhd" 20 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.157 ns + Longest register pin " "Info: + Longest register to pin delay is 3.157 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns decodeout~reg0 1 REG LCFF_X1_Y5_N25 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y5_N25; Fanout = 1; REG Node = 'decodeout~reg0'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { decodeout~reg0 } "NODE_NAME" } } { "miller_decoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_decoder.vhd" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.515 ns) + CELL(2.642 ns) 3.157 ns decodeout 2 PIN PIN_24 0 " "Info: 2: + IC(0.515 ns) + CELL(2.642 ns) = 3.157 ns; Loc. = PIN_24; Fanout = 0; PIN Node = 'decodeout'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.157 ns" { decodeout~reg0 decodeout } "NODE_NAME" } } { "miller_decoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_decoder.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.642 ns ( 83.69 % ) " "Info: Total cell delay = 2.642 ns ( 83.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.515 ns ( 16.31 % ) " "Info: Total interconnect delay = 0.515 ns ( 16.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.157 ns" { decodeout~reg0 decodeout } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.157 ns" { decodeout~reg0 {} decodeout {} } { 0.000ns 0.515ns } { 0.000ns 2.642ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.345 ns" { clk clk~clkctrl decodeout~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.345 ns" { clk {} clk~combout {} clk~clkctrl {} decodeout~reg0 {} } { 0.000ns 0.000ns 0.122ns 0.697ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.157 ns" { decodeout~reg0 decodeout } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.157 ns" { decodeout~reg0 {} decodeout {} } { 0.000ns 0.515ns } { 0.000ns 2.642ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "decodeout~reg0 encodein\[0\] clk -2.950 ns register " "Info: th for register \"decodeout~reg0\" (data pin = \"encodein\[0\]\", clock pin = \"clk\") is -2.950 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.345 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.345 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "miller_decoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_decoder.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 2 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "miller_decoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_decoder.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.697 ns) + CELL(0.537 ns) 2.345 ns decodeout~reg0 3 REG LCFF_X1_Y5_N25 1 " "Info: 3: + IC(0.697 ns) + CELL(0.537 ns) = 2.345 ns; Loc. = LCFF_X1_Y5_N25; Fanout = 1; REG Node = 'decodeout~reg0'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.234 ns" { clk~clkctrl decodeout~reg0 } "NODE_NAME" } } { "miller_decoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_decoder.vhd" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 65.07 % ) " "Info: Total cell delay = 1.526 ns ( 65.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.819 ns ( 34.93 % ) " "Info: Total interconnect delay = 0.819 ns ( 34.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.345 ns" { clk clk~clkctrl decodeout~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.345 ns" { clk {} clk~combout {} clk~clkctrl {} decodeout~reg0 {} } { 0.000ns 0.000ns 0.122ns 0.697ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "miller_decoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_decoder.vhd" 20 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.561 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.561 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.862 ns) 0.862 ns encodein\[0\] 1 PIN PIN_27 1 " "Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_27; Fanout = 1; PIN Node = 'encodein\[0\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { encodein[0] } "NODE_NAME" } } { "miller_decoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_decoder.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.465 ns) + CELL(0.150 ns) 5.477 ns process0~4 2 COMB LCCOMB_X1_Y5_N24 1 " "Info: 2: + IC(4.465 ns) + CELL(0.150 ns) = 5.477 ns; Loc. = LCCOMB_X1_Y5_N24; Fanout = 1; COMB Node = 'process0~4'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.615 ns" { encodein[0] process0~4 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 5.561 ns decodeout~reg0 3 REG LCFF_X1_Y5_N25 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 5.561 ns; Loc. = LCFF_X1_Y5_N25; Fanout = 1; REG Node = 'decodeout~reg0'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { process0~4 decodeout~reg0 } "NODE_NAME" } } { "miller_decoder.vhd" "" { Text "E:/通信原理/实验五/miller/miller_decoder.vhd" 20 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.096 ns ( 19.71 % ) " "Info: Total cell delay = 1.096 ns ( 19.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.465 ns ( 80.29 % ) " "Info: Total interconnect delay = 4.465 ns ( 80.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.561 ns" { encodein[0] process0~4 decodeout~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.561 ns" { encodein[0] {} encodein[0]~combout {} process0~4 {} decodeout~reg0 {} } { 0.000ns 0.000ns 4.465ns 0.000ns } { 0.000ns 0.862ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.345 ns" { clk clk~clkctrl decodeout~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.345 ns" { clk {} clk~combout {} clk~clkctrl {} decodeout~reg0 {} } { 0.000ns 0.000ns 0.122ns 0.697ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.561 ns" { encodein[0] process0~4 decodeout~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.561 ns" { encodein[0] {} encodein[0]~combout {} process0~4 {} decodeout~reg0 {} } { 0.000ns 0.000ns 4.465ns 0.000ns } { 0.000ns 0.862ns 0.150ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "122 " "Info: Peak virtual memory: 122 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu May 14 00:23:51 2009 " "Info: Processing ended: Thu May 14 00:23:51 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}