📄 __projnav.log
字号:
Project Navigator Auto-Make Log File-------------------------------------
Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling source file "vga_wb_slave.v"Compiling include file "vga_defines.v"Module <vga_wb_slave> compiledCompiling source file "vga_fifo.v"Module <vga_fifo> compiledCompiling source file "vga_wb_master.v"Module <vga_wb_master> compiledCompiling source file "generic_spram.v"Compiling include file "timescale.v"WARNING:HDLCompilers:38 - generic_spram.v line 80 Macro 'VENDOR_FPGA' redefinedCompiling source file "vga_csm_pb.v"Module <generic_spram> compiledModule <vga_csm_pb> compiledCompiling source file "vga_clkgen.v"Compiling include file "vga_defines.v"WARNING:HDLCompilers:38 - vga_defines.v line 72 Macro 'VENDOR_FPGA' redefinedWARNING:HDLCompilers:38 - vga_defines.v line 77 Macro 'VGA_12BIT_DVI' redefinedModule <vga_clkgen> compiledCompiling source file "vga_vtim.v"Compiling source file "vga_tgen.v"Module <vga_vtim> compiledModule <vga_tgen> compiledCompiling source file "vga_colproc.v"Compiling source file "vga_pgen.v"Compiling include file "vga_defines.v"WARNING:HDLCompilers:38 - vga_defines.v line 72 Macro 'VENDOR_FPGA' redefinedWARNING:HDLCompilers:38 - vga_defines.v line 77 Macro 'VGA_12BIT_DVI' redefinedModule <vga_colproc> compiledModule <vga_pgen> compiledCompiling source file "generic_dpram.v"WARNING:HDLCompilers:38 - generic_dpram.v line 107 Macro 'VENDOR_FPGA' redefinedCompiling source file "vga_fifo_dc.v"Module <generic_dpram> compiledModule <vga_fifo_dc> compiledCompiling source file "vga_enh_top.v"Compiling include file "vga_defines.v"WARNING:HDLCompilers:38 - vga_defines.v line 72 Macro 'VENDOR_FPGA' redefinedWARNING:HDLCompilers:38 - vga_defines.v line 77 Macro 'VGA_12BIT_DVI' redefinedModule <vga_enh_top> compiledNo errors in compilationAnalysis of file <vga_enh_top.prj> succeeded. Completed process "Check Syntax".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "vga_wb_slave.v"Compiling include file "vga_defines.v"Module <vga_wb_slave> compiledCompiling source file "vga_fifo.v"Module <vga_fifo> compiledCompiling source file "vga_wb_master.v"Module <vga_wb_master> compiledCompiling source file "generic_spram.v"Compiling include file "timescale.v"WARNING:HDLCompilers:38 - generic_spram.v line 80 Macro 'VENDOR_FPGA' redefinedCompiling source file "vga_csm_pb.v"Module <generic_spram> compiledModule <vga_csm_pb> compiledCompiling source file "vga_clkgen.v"Compiling include file "vga_defines.v"WARNING:HDLCompilers:38 - vga_defines.v line 72 Macro 'VENDOR_FPGA' redefinedWARNING:HDLCompilers:38 - vga_defines.v line 77 Macro 'VGA_12BIT_DVI' redefinedModule <vga_clkgen> compiledCompiling source file "vga_vtim.v"Compiling source file "vga_tgen.v"Module <vga_vtim> compiledModule <vga_tgen> compiledCompiling source file "vga_colproc.v"Compiling source file "vga_pgen.v"Compiling include file "vga_defines.v"WARNING:HDLCompilers:38 - vga_defines.v line 72 Macro 'VENDOR_FPGA' redefinedWARNING:HDLCompilers:38 - vga_defines.v line 77 Macro 'VGA_12BIT_DVI' redefinedModule <vga_colproc> compiledModule <vga_pgen> compiledCompiling source file "generic_dpram.v"WARNING:HDLCompilers:38 - generic_dpram.v line 107 Macro 'VENDOR_FPGA' redefinedCompiling source file "vga_fifo_dc.v"Module <generic_dpram> compiledModule <vga_fifo_dc> compiledCompiling source file "vga_enh_top.v"Compiling include file "vga_defines.v"WARNING:HDLCompilers:38 - vga_defines.v line 72 Macro 'VENDOR_FPGA' redefinedWARNING:HDLCompilers:38 - vga_defines.v line 77 Macro 'VGA_12BIT_DVI' redefinedModule <vga_enh_top> compiledNo errors in compilationAnalysis of file <vga_enh_top.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================WARNING:HDLCompilers:188 - vga_fifo.v line 131 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 132 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 132 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 133 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 133 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 134 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 134 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 134 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 135 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 135 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 136 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 136 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 137 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 137 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 138 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 138 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 139 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 140 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 140 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 141 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 141 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 142 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 142 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 142 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 131 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 132 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 132 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 133 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 133 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 134 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 134 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 134 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 135 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 135 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 136 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 136 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 137 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 137 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 138 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 138 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 139 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 140 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 140 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 141 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 141 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 142 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 142 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 142 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 131 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 132 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 132 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 133 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 133 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 134 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 134 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 134 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 135 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 135 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 136 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 136 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 137 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 137 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 138 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 138 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 139 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 140 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 140 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 141 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 141 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 142 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 142 Index in bit-select of vector reg 'q' is out of rangeWARNING:HDLCompilers:188 - vga_fifo.v line 142 Index in bit-select of vector reg 'q' is out of rangeAnalyzing top module <vga_enh_top>.WARNING:Xst:916 - vga_enh_top.v line 420: Delay is ignored for synthesis.WARNING:Xst:916 - vga_enh_top.v line 425: Delay is ignored for synthesis.WARNING:Xst:916 - vga_enh_top.v line 426: Delay is ignored for synthesis.WARNING:Xst:916 - vga_enh_top.v line 430: Delay is ignored for synthesis.WARNING:Xst:916 - vga_enh_top.v line 431: Delay is ignored for synthesis.ERROR:Xst:899 - vga_enh_top.v line 425: The logic for <sluint> does not match a known FF or Latch template.ERROR:Xst:899 - vga_enh_top.v line 426: The logic for <luint> does not match a known FF or Latch template. Found 2 error(s). Aborting synthesis.--> Total memory usage is 48688 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================Compiling source file "vga_wb_slave.v"Compiling include file "vga_defines.v"Module <vga_wb_slave> compiledCompiling source file "vga_fifo.v"Module <vga_fifo> compiledCompiling source file "vga_wb_master.v"Module <vga_wb_master> compiledCompiling source file "generic_spram.v"Compiling include file "timescale.v"WARNING:HDLCompilers:38 - generic_spram.v line 6 Macro 'VENDOR_FPGA' redefinedCompiling source file "vga_csm_pb.v"Module <generic_spram> compiledModule <vga_csm_pb> compiledCompiling source file "vga_clkgen.v"Compiling include file "vga_defines.v"WARNING:HDLCompilers:38 - vga_defines.v line 72 Macro 'VENDOR_FPGA' redefinedWARNING:HDLCompilers:38 - vga_defines.v line 77 Macro 'VGA_12BIT_DVI' redefinedModule <vga_clkgen> compiledCompiling source file "vga_tgen.v"Module <vga_tgen> compiledCompiling source file "vga_colproc.v"Compiling source file "vga_pgen.v"Compiling include file "vga_defines.v"WARNING:HDLCompilers:38 - vga_defines.v line 72 Macro 'VENDOR_FPGA' redefinedWARNING:HDLCompilers:38 - vga_defines.v line 77 Macro 'VGA_12BIT_DVI' redefinedModule <vga_colproc> compiledModule <vga_pgen> compiledCompiling source file "generic_dpram.v"WARNING:HDLCompilers:38 - generic_dpram.v line 6 Macro 'VENDOR_FPGA' redefinedCompiling source file "vga_fifo_dc.v"Module <generic_dpram> compiledModule <vga_fifo_dc> compiledCompiling source file "vga_enh_top.v"Compiling include file "vga_defines.v"WARNING:HDLCompilers:38 - vga_defines.v line 72 Macro 'VENDOR_FPGA' redefinedWARNING:HDLCompilers:38 - vga_defines.v line 77 Macro 'VGA_12BIT_DVI' redefinedModule <vga_enh_top> compiledNo errors in compilationAnalysis of file <vga_enh_top.prj> succeeded. Completed process "Check Syntax".
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -