count8.vhd

一个用VHDL编写的秒表程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity count8 is
	port(reset	:in std_logic;
		clk		:in std_logic;
		sel		:out std_logic_vector(2 downto 0)
		);
end count8;
architecture rtl of count8 is
	signal sel_temp:std_logic_vector(2 downto 0);
begin
	process(clk)
	begin
		if(clk'event and clk='1')then
			if(reset='1')then
				sel_temp<=(others=>'0');
			elsif(sel_temp="111")then
				sel_temp<=(others=>'0');
			else
				sel_temp<=sel_temp+1;
			end if;
		end if;
		sel<=sel_temp;
	end process;
end rtl;