display.vhd

一个用VHDL编写的秒表程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity display is
	port(sysreset	:in std_logic;
			clk		:in std_logic;
			hr10	:in std_logic_vector(3 downto 0);
			hr		:in std_logic_vector(3 downto 0);
			min10	:in std_logic_vector(2 downto 0);
			min 	:in std_logic_vector(3 downto 0);
            sec10	:in std_logic_vector(2 downto 0);
            sec 	:in std_logic_vector(3 downto 0);
            sec01	:in std_logic_vector(3 downto 0);
            sec001	:in std_logic_vector(3 downto 0);
			choose	:out std_logic_vector(7 downto 0); 
			segment	:out std_logic_vector(6 downto 0)    
			);
end display;
architecture rtl of display is
	component count8
		port(reset	:in std_logic;
			clk		:in std_logic;
			sel		:out std_logic_vector(2 downto 0)
			);
	end component;
	
	component choose_decode
		port(sel	:in std_logic_vector(2 downto 0);
		choose	:out std_logic_vector(7 downto 0)
		);
	end component;
	
	component time_choose
		port(sel	:in std_logic_vector(2 downto 0);		
		hr10	:in std_logic_vector(3 downto 0);
		hr		:in std_logic_vector(3 downto 0);
		min10	:in std_logic_vector(2 downto 0);
		min		:in std_logic_vector(3 downto 0);
		sec10	:in std_logic_vector(2 downto 0);
		sec		:in std_logic_vector(3 downto 0);
		sec01	:in std_logic_vector(3 downto 0);
		sec001	:in std_logic_vector(3 downto 0);
		q		:out std_logic_vector(3 downto 0)
		);
	end component;
	
	component seg7
		port(q	:in std_logic_vector(3 downto 0);
		segment:out std_logic_vector(6 downto 0)
		);
end component;

	signal sel	:std_logic_vector(2 downto 0);
	signal q	:std_logic_vector(3 downto 0);
	signal choose_temp	:std_logic_vector(7 downto 0);
	signal segment_temp	:std_logic_vector(6 downto 0);

begin
	u0:count8
		port map(sysreset,clk,sel);
	u1:choose_decode
		port map(sel,choose_temp);
	u2:time_choose
		port map(sel,hr10,hr,min10,min,sec10,sec,sec01,sec001,q);
	u3:seg7
		port map(q,segment_temp);
	choose<=choose_temp;
	segment<=segment_temp;
end rtl;