📄 count10.rpt
字号:
- 1 - A 01 AND2 s 1 1 0 3 ~130~1
- 4 - A 01 OR2 0 4 0 1 :130
- 2 - A 01 OR2 0 4 0 1 :142
- 2 - A 02 OR2 0 3 0 1 :151
- 3 - A 01 AND2 1 1 1 0 :227
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\work\max+plus_work\stopwatch\count10.rpt
count10
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 5/ 48( 10%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\work\max+plus_work\stopwatch\count10.rpt
count10
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 clk
Device-Specific Information: d:\work\max+plus_work\stopwatch\count10.rpt
count10
** EQUATIONS **
clk : INPUT;
enable : INPUT;
reset : INPUT;
-- Node name is 'cout'
-- Equation name is 'cout', type is output
cout = _LC3_A1;
-- Node name is ':12' = 'q_temp0'
-- Equation name is 'q_temp0', location is LC1_A2, type is buried.
q_temp0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !enable & q_temp0 & !reset
# enable & !q_temp0 & !reset;
-- Node name is ':11' = 'q_temp1'
-- Equation name is 'q_temp1', location is LC3_A2, type is buried.
q_temp1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC2_A2 & !reset
# !enable & q_temp1 & !reset;
-- Node name is ':10' = 'q_temp2'
-- Equation name is 'q_temp2', location is LC5_A1, type is buried.
q_temp2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC2_A1 & !reset
# !enable & q_temp2 & !reset;
-- Node name is ':9' = 'q_temp3'
-- Equation name is 'q_temp3', location is LC7_A1, type is buried.
q_temp3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC4_A1 & !reset
# !enable & q_temp3 & !reset;
-- Node name is 'q0'
-- Equation name is 'q0', type is output
q0 = q_temp0;
-- Node name is 'q1'
-- Equation name is 'q1', type is output
q1 = q_temp1;
-- Node name is 'q2'
-- Equation name is 'q2', type is output
q2 = q_temp2;
-- Node name is 'q3'
-- Equation name is 'q3', type is output
q3 = q_temp3;
-- Node name is '|LPM_ADD_SUB:77|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_A1', type is buried
_LC8_A1 = LCELL( _EQ005);
_EQ005 = q_temp0 & q_temp1;
-- Node name is ':52'
-- Equation name is '_LC6_A1', type is buried
!_LC6_A1 = _LC6_A1~NOT;
_LC6_A1~NOT = LCELL( _EQ006);
_EQ006 = q_temp2
# q_temp1
# !q_temp3
# !q_temp0;
-- Node name is '~130~1'
-- Equation name is '~130~1', location is LC1_A1, type is buried.
-- synthesized logic cell
_LC1_A1 = LCELL( _EQ007);
_EQ007 = enable & !_LC6_A1;
-- Node name is ':130'
-- Equation name is '_LC4_A1', type is buried
_LC4_A1 = LCELL( _EQ008);
_EQ008 = _LC1_A1 & !_LC8_A1 & q_temp3
# _LC1_A1 & !q_temp2 & q_temp3
# _LC1_A1 & _LC8_A1 & q_temp2 & !q_temp3;
-- Node name is ':142'
-- Equation name is '_LC2_A1', type is buried
_LC2_A1 = LCELL( _EQ009);
_EQ009 = _LC1_A1 & !q_temp1 & q_temp2
# _LC1_A1 & !q_temp0 & q_temp2
# _LC1_A1 & q_temp0 & q_temp1 & !q_temp2;
-- Node name is ':151'
-- Equation name is '_LC2_A2', type is buried
_LC2_A2 = LCELL( _EQ010);
_EQ010 = _LC1_A1 & !q_temp0 & q_temp1
# _LC1_A1 & q_temp0 & !q_temp1;
-- Node name is ':227'
-- Equation name is '_LC3_A1', type is buried
_LC3_A1 = LCELL( _EQ011);
_EQ011 = enable & _LC6_A1;
Project Information d:\work\max+plus_work\stopwatch\count10.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 10,769K
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