clk_div.vhd

一个用VHDL编写的秒表程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity clk_div is
	port(sysreset	:in std_logic;
		clk	:in std_logic;
		clk0:out std_logic;
		clk1:out std_logic
		);
end clk_div;

architecture rtl of clk_div is
	component clk_div10
		port(clk	:in std_logic;
			reset	:in std_logic;
			clk_div	:out std_logic
			);
	end component;
	component clk_div4
		port(clk	:in std_logic;
			reset	:in std_logic;
			clk_div	:out std_logic
			);
	end component;
	
	signal clk0_temp:std_logic;
	signal clk1_temp:std_logic;
begin
	u0:clk_div10
		port map(clk,sysreset,clk0_temp);
	u1:clk_div4
		port map(clk0_temp,sysreset,clk1_temp);
	clk0<=clk0_temp;
	clk1<=clk0_temp and clk1_temp;
end rtl;