📄 choose_decode.rpt
字号:
- 5 - A 03 AND2 3 0 1 0 :282
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\work\max+plus_work\stopwatch\choose_decode.rpt
choose_decode
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/ 96( 4%) 4/ 48( 8%) 0/ 48( 0%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\work\max+plus_work\stopwatch\choose_decode.rpt
choose_decode
** EQUATIONS **
sel0 : INPUT;
sel1 : INPUT;
sel2 : INPUT;
-- Node name is 'choose0'
-- Equation name is 'choose0', type is output
choose0 = _LC1_A4;
-- Node name is 'choose1'
-- Equation name is 'choose1', type is output
choose1 = _LC3_A5;
-- Node name is 'choose2'
-- Equation name is 'choose2', type is output
choose2 = _LC5_A6;
-- Node name is 'choose3'
-- Equation name is 'choose3', type is output
choose3 = _LC7_A1;
-- Node name is 'choose4'
-- Equation name is 'choose4', type is output
choose4 = _LC1_A1;
-- Node name is 'choose5'
-- Equation name is 'choose5', type is output
choose5 = _LC3_A1;
-- Node name is 'choose6'
-- Equation name is 'choose6', type is output
choose6 = _LC3_A2;
-- Node name is 'choose7'
-- Equation name is 'choose7', type is output
choose7 = _LC5_A3;
-- Node name is ':217'
-- Equation name is '_LC3_A2', type is buried
!_LC3_A2 = _LC3_A2~NOT;
_LC3_A2~NOT = LCELL( _EQ001);
_EQ001 = !sel1
# sel0
# !sel2;
-- Node name is ':227'
-- Equation name is '_LC3_A1', type is buried
!_LC3_A1 = _LC3_A1~NOT;
_LC3_A1~NOT = LCELL( _EQ002);
_EQ002 = sel1
# !sel0
# !sel2;
-- Node name is ':237'
-- Equation name is '_LC1_A1', type is buried
!_LC1_A1 = _LC1_A1~NOT;
_LC1_A1~NOT = LCELL( _EQ003);
_EQ003 = sel1
# sel0
# !sel2;
-- Node name is ':247'
-- Equation name is '_LC7_A1', type is buried
!_LC7_A1 = _LC7_A1~NOT;
_LC7_A1~NOT = LCELL( _EQ004);
_EQ004 = !sel1
# !sel0
# sel2;
-- Node name is ':257'
-- Equation name is '_LC5_A6', type is buried
!_LC5_A6 = _LC5_A6~NOT;
_LC5_A6~NOT = LCELL( _EQ005);
_EQ005 = !sel1
# sel0
# sel2;
-- Node name is ':267'
-- Equation name is '_LC3_A5', type is buried
!_LC3_A5 = _LC3_A5~NOT;
_LC3_A5~NOT = LCELL( _EQ006);
_EQ006 = sel1
# !sel0
# sel2;
-- Node name is ':277'
-- Equation name is '_LC1_A4', type is buried
!_LC1_A4 = _LC1_A4~NOT;
_LC1_A4~NOT = LCELL( _EQ007);
_EQ007 = sel2
# sel1
# sel0;
-- Node name is ':282'
-- Equation name is '_LC5_A3', type is buried
_LC5_A3 = LCELL( _EQ008);
_EQ008 = sel0 & sel1 & sel2;
Project Information d:\work\max+plus_work\stopwatch\choose_decode.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,458K
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