control1.vhd

一个用VHDL编写的秒表程序

library ieee;
use ieee.std_logic_1164.all;

entity control1 is
	port(sysreset	:in std_logic;
		reset0	:in std_logic;
		on_off0	:in std_logic;
		clk0	:in std_logic;
		enable	:out std_logic
		);
end control1;

architecture rtl of control1 is
	signal stroble:std_logic;
begin
	process(sysreset,reset0,on_off0)
	begin
		if(sysreset='1' OR reset0='1')then
			stroble<='0';
		elsif(on_off0'event and on_off0='1')then
			stroble<=NOT stroble;
		end if;
	end process;
	enable<=clk0 and stroble;
end rtl;