📄 display.rpt
字号:
-- Node name is '|seg7:u3|:437'
-- Equation name is '_LC5_B7', type is buried
_LC5_B7 = LCELL( _EQ015);
_EQ015 = _LC2_B11 & !_LC3_B3
# !_LC1_B11 & !_LC3_B3
# _LC1_B11 & _LC8_A2
# _LC2_B11 & _LC8_A2
# !_LC3_B3 & _LC8_A2;
-- Node name is '|seg7:u3|:470'
-- Equation name is '_LC1_B9', type is buried
_LC1_B9 = LCELL( _EQ016);
_EQ016 = _LC8_A2
# _LC2_B11 & !_LC3_B3
# !_LC1_B11 & _LC2_B11
# !_LC1_B11 & !_LC3_B3
# _LC1_B11 & !_LC2_B11 & _LC3_B3;
-- Node name is '|seg7:u3|:503'
-- Equation name is '_LC6_B8', type is buried
_LC6_B8 = LCELL( _EQ017);
_EQ017 = !_LC2_B11 & !_LC8_A2
# !_LC1_B11 & !_LC2_B11
# _LC3_B3 & !_LC8_A2
# _LC1_B11 & !_LC8_A2;
-- Node name is '|seg7:u3|:526'
-- Equation name is '_LC4_B4', type is buried
_LC4_B4 = LCELL( _EQ018);
_EQ018 = _LC1_B11 & _LC2_B11 & _LC3_B3 & !_LC8_A2
# !_LC1_B11 & !_LC2_B11 & _LC8_A2;
-- Node name is '|seg7:u3|~536~1'
-- Equation name is '_LC3_B4', type is buried
-- synthesized logic cell
_LC3_B4 = LCELL( _EQ019);
_EQ019 = !_LC2_B11 & !_LC3_B3 & !_LC8_A2;
-- Node name is '|seg7:u3|:536'
-- Equation name is '_LC2_B4', type is buried
_LC2_B4 = LCELL( _EQ020);
_EQ020 = _LC4_B4
# !_LC1_B4
# _LC3_B4;
-- Node name is '|seg7:u3|:569'
-- Equation name is '_LC2_B10', type is buried
_LC2_B10 = LCELL( _EQ021);
_EQ021 = _LC2_B11
# _LC8_A2
# _LC1_B11 & _LC3_B3
# !_LC1_B11 & !_LC3_B3;
-- Node name is '|time_choose:u2|:226'
-- Equation name is '_LC6_A1', type is buried
_LC6_A1 = LCELL( _EQ022);
_EQ022 = hr103 & !_LC7_A1
# hr3 & _LC7_A1;
-- Node name is '|time_choose:u2|:246'
-- Equation name is '_LC8_A1', type is buried
_LC8_A1 = LCELL( _EQ023);
_EQ023 = !_LC3_A1 & !_LC5_A1 & _LC6_A1
# _LC5_A1 & min3;
-- Node name is '|time_choose:u2|:266'
-- Equation name is '_LC2_A1', type is buried
_LC2_A1 = LCELL( _EQ024);
_EQ024 = !_LC1_A1 & !_LC4_A1 & _LC8_A1
# _LC1_A1 & sec3;
-- Node name is '|time_choose:u2|:276'
-- Equation name is '_LC1_A2', type is buried
_LC1_A2 = LCELL( _EQ025);
_EQ025 = _LC2_A1 & !_LC2_A2
# _LC2_A2 & sec013;
-- Node name is '|time_choose:u2|:286'
-- Equation name is '_LC8_A2', type is buried
_LC8_A2 = LCELL( _EQ026);
_EQ026 = _LC1_A2 & !_LC5_A2
# _LC5_A2 & sec0013;
-- Node name is '|time_choose:u2|:292'
-- Equation name is '_LC1_B13', type is buried
!_LC1_B13 = _LC1_B13~NOT;
_LC1_B13~NOT = LCELL( _EQ027);
_EQ027 = !hr2 & !hr102
# !hr2 & _LC7_A1
# !hr102 & !_LC7_A1;
-- Node name is '|time_choose:u2|:295'
-- Equation name is '_LC6_B12', type is buried
!_LC6_B12 = _LC6_B12~NOT;
_LC6_B12~NOT = LCELL( _EQ028);
_EQ028 = !_LC1_B13 & !min102
# !_LC1_B13 & !_LC3_A1
# _LC3_A1 & !min102;
-- Node name is '|time_choose:u2|:298'
-- Equation name is '_LC8_B12', type is buried
!_LC8_B12 = _LC8_B12~NOT;
_LC8_B12~NOT = LCELL( _EQ029);
_EQ029 = !_LC6_B12 & !min2
# _LC5_A1 & !min2
# !_LC5_A1 & !_LC6_B12;
-- Node name is '|time_choose:u2|:301'
-- Equation name is '_LC7_B12', type is buried
!_LC7_B12 = _LC7_B12~NOT;
_LC7_B12~NOT = LCELL( _EQ030);
_EQ030 = !_LC8_B12 & !sec102
# _LC4_A1 & !sec102
# !_LC4_A1 & !_LC8_B12;
-- Node name is '|time_choose:u2|:304'
-- Equation name is '_LC1_B12', type is buried
!_LC1_B12 = _LC1_B12~NOT;
_LC1_B12~NOT = LCELL( _EQ031);
_EQ031 = !_LC7_B12 & !sec2
# _LC1_A1 & !sec2
# !_LC1_A1 & !_LC7_B12;
-- Node name is '|time_choose:u2|:307'
-- Equation name is '_LC4_B11', type is buried
!_LC4_B11 = _LC4_B11~NOT;
_LC4_B11~NOT = LCELL( _EQ032);
_EQ032 = !_LC1_B12 & !sec012
# _LC2_A2 & !sec012
# !_LC1_B12 & !_LC2_A2;
-- Node name is '|time_choose:u2|:310'
-- Equation name is '_LC1_B11', type is buried
!_LC1_B11 = _LC1_B11~NOT;
_LC1_B11~NOT = LCELL( _EQ033);
_EQ033 = !_LC4_B11 & !sec0012
# _LC5_A2 & !sec0012
# !_LC4_B11 & !_LC5_A2;
-- Node name is '|time_choose:u2|:316'
-- Equation name is '_LC1_B2', type is buried
_LC1_B2 = LCELL( _EQ034);
_EQ034 = hr101 & !_LC7_A1
# hr1 & _LC7_A1;
-- Node name is '|time_choose:u2|:319'
-- Equation name is '_LC2_B12', type is buried
_LC2_B12 = LCELL( _EQ035);
_EQ035 = _LC3_A1 & min101
# _LC1_B2 & !_LC3_A1;
-- Node name is '|time_choose:u2|:322'
-- Equation name is '_LC4_B12', type is buried
_LC4_B12 = LCELL( _EQ036);
_EQ036 = _LC2_B12 & !_LC5_A1
# _LC5_A1 & min1;
-- Node name is '|time_choose:u2|:325'
-- Equation name is '_LC5_B12', type is buried
_LC5_B12 = LCELL( _EQ037);
_EQ037 = !_LC4_A1 & _LC4_B12
# _LC4_A1 & sec101;
-- Node name is '|time_choose:u2|:328'
-- Equation name is '_LC3_B12', type is buried
_LC3_B12 = LCELL( _EQ038);
_EQ038 = !_LC1_A1 & _LC5_B12
# _LC1_A1 & sec1;
-- Node name is '|time_choose:u2|:331'
-- Equation name is '_LC3_B11', type is buried
_LC3_B11 = LCELL( _EQ039);
_EQ039 = !_LC2_A2 & _LC3_B12
# _LC2_A2 & sec011;
-- Node name is '|time_choose:u2|:334'
-- Equation name is '_LC2_B11', type is buried
_LC2_B11 = LCELL( _EQ040);
_EQ040 = _LC3_B11 & !_LC5_A2
# _LC5_A2 & sec0011;
-- Node name is '|time_choose:u2|:340'
-- Equation name is '_LC7_B3', type is buried
_LC7_B3 = LCELL( _EQ041);
_EQ041 = hr100 & !_LC7_A1
# hr0 & _LC7_A1;
-- Node name is '|time_choose:u2|:343'
-- Equation name is '_LC6_B3', type is buried
_LC6_B3 = LCELL( _EQ042);
_EQ042 = _LC3_A1 & min100
# !_LC3_A1 & _LC7_B3;
-- Node name is '|time_choose:u2|:346'
-- Equation name is '_LC5_B3', type is buried
_LC5_B3 = LCELL( _EQ043);
_EQ043 = !_LC5_A1 & _LC6_B3
# _LC5_A1 & min0;
-- Node name is '|time_choose:u2|:349'
-- Equation name is '_LC4_B3', type is buried
_LC4_B3 = LCELL( _EQ044);
_EQ044 = !_LC4_A1 & _LC5_B3
# _LC4_A1 & sec100;
-- Node name is '|time_choose:u2|:352'
-- Equation name is '_LC2_B3', type is buried
_LC2_B3 = LCELL( _EQ045);
_EQ045 = !_LC1_A1 & _LC4_B3
# _LC1_A1 & sec0;
-- Node name is '|time_choose:u2|:355'
-- Equation name is '_LC1_B3', type is buried
_LC1_B3 = LCELL( _EQ046);
_EQ046 = !_LC2_A2 & _LC2_B3
# _LC2_A2 & sec010;
-- Node name is '|time_choose:u2|:358'
-- Equation name is '_LC3_B3', type is buried
_LC3_B3 = LCELL( _EQ047);
_EQ047 = _LC1_B3 & !_LC5_A2
# _LC5_A2 & sec0010;
Project Information d:\work\max+plus_work\stopwatch\display.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 11,586K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -