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📄 display.rpt

📁 一个用VHDL编写的秒表程序
💻 RPT
📖 第 1 页 / 共 3 页
字号:
 IOC     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   -      7     -    A    01        OR2        !       0    3    1    4  |choose_decode:u1|:217
   -      3     -    A    01        OR2        !       0    3    1    4  |choose_decode:u1|:227
   -      5     -    A    01        OR2        !       0    3    1    4  |choose_decode:u1|:237
   -      4     -    A    01        OR2        !       0    3    1    4  |choose_decode:u1|:247
   -      1     -    A    01        OR2        !       0    3    1    4  |choose_decode:u1|:257
   -      2     -    A    02        OR2        !       0    3    1    4  |choose_decode:u1|:267
   -      5     -    A    02        OR2        !       0    3    1    4  |choose_decode:u1|:277
   -      1     -    A    03       AND2                0    3    1    0  |choose_decode:u1|:282
   -      1     -    A    11       DFFE   +            1    2    0    8  |count8:u0|sel_temp2 (|count8:u0|:6)
   -      1     -    A    12       DFFE   +            1    1    0    9  |count8:u0|sel_temp1 (|count8:u0|:7)
   -      1     -    A    04       DFFE   +            1    0    0   10  |count8:u0|sel_temp0 (|count8:u0|:8)
   -      7     -    B    05        OR2                0    4    1    0  |seg7:u3|:373
   -      2     -    B    06        OR2                0    4    1    0  |seg7:u3|:404
   -      1     -    B    04        OR2        !       0    4    0    1  |seg7:u3|:406
   -      5     -    B    07        OR2                0    4    1    0  |seg7:u3|:437
   -      1     -    B    09        OR2                0    4    1    0  |seg7:u3|:470
   -      6     -    B    08        OR2                0    4    1    0  |seg7:u3|:503
   -      4     -    B    04        OR2                0    4    0    1  |seg7:u3|:526
   -      3     -    B    04       AND2    s           0    3    0    1  |seg7:u3|~536~1
   -      2     -    B    04        OR2                0    3    1    0  |seg7:u3|:536
   -      2     -    B    10        OR2                0    4    1    0  |seg7:u3|:569
   -      6     -    A    01        OR2                2    1    0    1  |time_choose:u2|:226
   -      8     -    A    01        OR2                1    3    0    1  |time_choose:u2|:246
   -      2     -    A    01        OR2                1    3    0    1  |time_choose:u2|:266
   -      1     -    A    02        OR2                1    2    0    1  |time_choose:u2|:276
   -      8     -    A    02        OR2                1    2    0    9  |time_choose:u2|:286
   -      1     -    B    13        OR2        !       2    1    0    1  |time_choose:u2|:292
   -      6     -    B    12        OR2        !       1    2    0    1  |time_choose:u2|:295
   -      8     -    B    12        OR2        !       1    2    0    1  |time_choose:u2|:298
   -      7     -    B    12        OR2        !       1    2    0    1  |time_choose:u2|:301
   -      1     -    B    12        OR2        !       1    2    0    1  |time_choose:u2|:304
   -      4     -    B    11        OR2        !       1    2    0    1  |time_choose:u2|:307
   -      1     -    B    11        OR2        !       1    2    0    8  |time_choose:u2|:310
   -      1     -    B    02        OR2                2    1    0    1  |time_choose:u2|:316
   -      2     -    B    12        OR2                1    2    0    1  |time_choose:u2|:319
   -      4     -    B    12        OR2                1    2    0    1  |time_choose:u2|:322
   -      5     -    B    12        OR2                1    2    0    1  |time_choose:u2|:325
   -      3     -    B    12        OR2                1    2    0    1  |time_choose:u2|:328
   -      3     -    B    11        OR2                1    2    0    1  |time_choose:u2|:331
   -      2     -    B    11        OR2                1    2    0    9  |time_choose:u2|:334
   -      7     -    B    03        OR2                2    1    0    1  |time_choose:u2|:340
   -      6     -    B    03        OR2                1    2    0    1  |time_choose:u2|:343
   -      5     -    B    03        OR2                1    2    0    1  |time_choose:u2|:346
   -      4     -    B    03        OR2                1    2    0    1  |time_choose:u2|:349
   -      2     -    B    03        OR2                1    2    0    1  |time_choose:u2|:352
   -      1     -    B    03        OR2                1    2    0    1  |time_choose:u2|:355
   -      3     -    B    03        OR2                1    2    0    9  |time_choose:u2|:358


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:       d:\work\max+plus_work\stopwatch\display.rpt
display

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       6/ 96(  6%)     7/ 48( 14%)     0/ 48(  0%)    6/16( 37%)      3/16( 18%)     0/16(  0%)
B:      15/ 96( 15%)    22/ 48( 45%)     0/ 48(  0%)    9/16( 56%)      0/16(  0%)     0/16(  0%)
C:       5/ 96(  5%)     4/ 48(  8%)     0/ 48(  0%)    0/16(  0%)      9/16( 56%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      6/24( 25%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
02:      5/24( 20%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
03:      3/24( 12%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
04:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
05:      3/24( 12%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
06:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
07:      3/24( 12%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
10:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
11:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:       d:\work\max+plus_work\stopwatch\display.rpt
display

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT        3         clk


Device-Specific Information:       d:\work\max+plus_work\stopwatch\display.rpt
display

** EQUATIONS **

clk      : INPUT;
hr0      : INPUT;
hr1      : INPUT;
hr2      : INPUT;
hr3      : INPUT;
hr100    : INPUT;
hr101    : INPUT;
hr102    : INPUT;
hr103    : INPUT;
min0     : INPUT;
min1     : INPUT;
min2     : INPUT;
min3     : INPUT;
min100   : INPUT;
min101   : INPUT;
min102   : INPUT;
sec0     : INPUT;
sec1     : INPUT;
sec2     : INPUT;
sec3     : INPUT;
sec0010  : INPUT;
sec010   : INPUT;
sec0011  : INPUT;
sec011   : INPUT;
sec0012  : INPUT;
sec012   : INPUT;
sec0013  : INPUT;
sec013   : INPUT;
sec100   : INPUT;
sec101   : INPUT;
sec102   : INPUT;
sysreset : INPUT;

-- Node name is 'choose0' 
-- Equation name is 'choose0', type is output 
choose0  =  _LC5_A2;

-- Node name is 'choose1' 
-- Equation name is 'choose1', type is output 
choose1  =  _LC2_A2;

-- Node name is 'choose2' 
-- Equation name is 'choose2', type is output 
choose2  =  _LC1_A1;

-- Node name is 'choose3' 
-- Equation name is 'choose3', type is output 
choose3  =  _LC4_A1;

-- Node name is 'choose4' 
-- Equation name is 'choose4', type is output 
choose4  =  _LC5_A1;

-- Node name is 'choose5' 
-- Equation name is 'choose5', type is output 
choose5  =  _LC3_A1;

-- Node name is 'choose6' 
-- Equation name is 'choose6', type is output 
choose6  =  _LC7_A1;

-- Node name is 'choose7' 
-- Equation name is 'choose7', type is output 
choose7  =  _LC1_A3;

-- Node name is 'segment0' 
-- Equation name is 'segment0', type is output 
segment0 =  _LC2_B10;

-- Node name is 'segment1' 
-- Equation name is 'segment1', type is output 
segment1 =  _LC2_B4;

-- Node name is 'segment2' 
-- Equation name is 'segment2', type is output 
segment2 =  _LC6_B8;

-- Node name is 'segment3' 
-- Equation name is 'segment3', type is output 
segment3 =  _LC1_B9;

-- Node name is 'segment4' 
-- Equation name is 'segment4', type is output 
segment4 =  _LC5_B7;

-- Node name is 'segment5' 
-- Equation name is 'segment5', type is output 
segment5 =  _LC2_B6;

-- Node name is 'segment6' 
-- Equation name is 'segment6', type is output 
segment6 =  _LC7_B5;

-- Node name is '|choose_decode:u1|:217' 
-- Equation name is '_LC7_A1', type is buried 
!_LC7_A1 = _LC7_A1~NOT;
_LC7_A1~NOT = LCELL( _EQ001);
  _EQ001 =  _LC1_A4
         # !_LC1_A12
         # !_LC1_A11;

-- Node name is '|choose_decode:u1|:227' 
-- Equation name is '_LC3_A1', type is buried 
!_LC3_A1 = _LC3_A1~NOT;
_LC3_A1~NOT = LCELL( _EQ002);
  _EQ002 = !_LC1_A4
         #  _LC1_A12
         # !_LC1_A11;

-- Node name is '|choose_decode:u1|:237' 
-- Equation name is '_LC5_A1', type is buried 
!_LC5_A1 = _LC5_A1~NOT;
_LC5_A1~NOT = LCELL( _EQ003);
  _EQ003 =  _LC1_A4
         #  _LC1_A12
         # !_LC1_A11;

-- Node name is '|choose_decode:u1|:247' 
-- Equation name is '_LC4_A1', type is buried 
!_LC4_A1 = _LC4_A1~NOT;
_LC4_A1~NOT = LCELL( _EQ004);
  _EQ004 = !_LC1_A4
         # !_LC1_A12
         #  _LC1_A11;

-- Node name is '|choose_decode:u1|:257' 
-- Equation name is '_LC1_A1', type is buried 
!_LC1_A1 = _LC1_A1~NOT;
_LC1_A1~NOT = LCELL( _EQ005);
  _EQ005 =  _LC1_A4
         # !_LC1_A12
         #  _LC1_A11;

-- Node name is '|choose_decode:u1|:267' 
-- Equation name is '_LC2_A2', type is buried 
!_LC2_A2 = _LC2_A2~NOT;
_LC2_A2~NOT = LCELL( _EQ006);
  _EQ006 = !_LC1_A4
         #  _LC1_A12
         #  _LC1_A11;

-- Node name is '|choose_decode:u1|:277' 
-- Equation name is '_LC5_A2', type is buried 
!_LC5_A2 = _LC5_A2~NOT;
_LC5_A2~NOT = LCELL( _EQ007);
  _EQ007 =  _LC1_A4
         #  _LC1_A12
         #  _LC1_A11;

-- Node name is '|choose_decode:u1|:282' 
-- Equation name is '_LC1_A3', type is buried 
_LC1_A3  = LCELL( _EQ008);
  _EQ008 =  _LC1_A4 &  _LC1_A11 &  _LC1_A12;

-- Node name is '|count8:u0|:8' = '|count8:u0|sel_temp0' 
-- Equation name is '_LC1_A4', type is buried 
_LC1_A4  = DFFE( _EQ009, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ009 = !_LC1_A4 & !sysreset;

-- Node name is '|count8:u0|:7' = '|count8:u0|sel_temp1' 
-- Equation name is '_LC1_A12', type is buried 
_LC1_A12 = DFFE( _EQ010, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ010 =  _LC1_A4 & !_LC1_A12 & !sysreset
         # !_LC1_A4 &  _LC1_A12 & !sysreset;

-- Node name is '|count8:u0|:6' = '|count8:u0|sel_temp2' 
-- Equation name is '_LC1_A11', type is buried 
_LC1_A11 = DFFE( _EQ011, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ011 = !_LC1_A4 &  _LC1_A11 & !sysreset
         #  _LC1_A11 & !_LC1_A12 & !sysreset
         #  _LC1_A4 & !_LC1_A11 &  _LC1_A12 & !sysreset;

-- Node name is '|seg7:u3|:373' 
-- Equation name is '_LC7_B5', type is buried 
_LC7_B5  = LCELL( _EQ012);
  _EQ012 =  _LC8_A2
         #  _LC1_B11 & !_LC2_B11
         #  _LC1_B11 & !_LC3_B3
         #  _LC2_B11 & !_LC3_B3
         # !_LC1_B11 &  _LC2_B11;

-- Node name is '|seg7:u3|:404' 
-- Equation name is '_LC2_B6', type is buried 
_LC2_B6  = LCELL( _EQ013);
  _EQ013 =  _LC8_A2
         #  _LC1_B11
         # !_LC2_B11 & !_LC3_B3;

-- Node name is '|seg7:u3|:406' 
-- Equation name is '_LC1_B4', type is buried 
!_LC1_B4 = _LC1_B4~NOT;
_LC1_B4~NOT = LCELL( _EQ014);
  _EQ014 = !_LC1_B11 &  _LC2_B11 & !_LC8_A2
         # !_LC1_B11 &  _LC3_B3 & !_LC8_A2;

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