clk_div.fit

一个用VHDL编写的秒表程序

-- MAX+plus II Compiler Fit File      
-- Version 9.23 3/19/99               
-- Compiled: 02/20/2009 22:24:52      

-- Copyright (C) 1988-1999 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "clk_div"
BEGIN

    DEVICE = "EPF10K10LC84-3";

    "clk"                          : INPUT_PIN  = 43     ;
    "sysreset"                     : INPUT_PIN  = 84     ;
    "clk0"                         : OUTPUT_PIN = 16     ;
    "clk1"                         : OUTPUT_PIN = 17     ;
    "|clk_div4:u1|:3"              : LOCATION   = LC1_A1 ;
    "|clk_div4:u1|:5"              : LOCATION   = LC2_A1 ;  -- |clk_div4:u1|count1
    "|clk_div4:u1|:6"              : LOCATION   = LC4_A1 ;  -- |clk_div4:u1|count0
    "|clk_div10:u0|LPM_ADD_SUB:66|addcore:adder|:55" : LOCATION   = LC3_A2 ;
    "|clk_div10:u0|:3"             : LOCATION   = LC1_A2 ;
    "|clk_div10:u0|:5"             : LOCATION   = LC2_A2 ;  -- |clk_div10:u0|count3
    "|clk_div10:u0|:6"             : LOCATION   = LC8_A2 ;  -- |clk_div10:u0|count2
    "|clk_div10:u0|:7"             : LOCATION   = LC7_A2 ;  -- |clk_div10:u0|count1
    "|clk_div10:u0|:8"             : LOCATION   = LC6_A2 ;  -- |clk_div10:u0|count0
    "|clk_div10:u0|:33"            : LOCATION   = LC5_A2 ;
    "|clk_div10:u0|~92~1"          : LOCATION   = LC4_A2 ;
    ":8"                           : LOCATION   = LC3_A1 ;

END;

INTERNAL_INFO "clk_div"
BEGIN
	DEVICE = EPF10K10LC84-3;
    OD5P43  : LORAX = "1:FB5->LC1_A2,->LC2_A2,->LC8_A2,->LC7_A2,->LC6_A2|";
    LC1_A2  : LORAX = "1:MSW0R0C1,HHL23R0->OH8R0P16|2:PA1R0C0->LC1_A1,->LC2_A1,->LC4_A1,->LC3_A1||";
    OD0P84  : LORAX = "1:FB0|2:FH0R0|3:PA0R0C1->LC8_A2,->LC7_A2,->LC6_A2,->LC4_A2|,3:PA0R0C0->LC2_A1,->LC4_A1|||";
    LC3_A1  : LORAX = "1:MSW2R0C0,HHL3R0->OH10R0P17|";
	LC1_A1  : LORAX2 = "X, X, LC2_A1, LC4_A1";
	LC2_A1  : LORAX2 = "X, OD0P84, LC2_A1, LC4_A1";
	LC4_A1  : LORAX2 = "X, X, OD0P84, LC4_A1";
	LC3_A2  : LORAX2 = "X, X, LC7_A2, LC6_A2";
	LC1_A2  : LORAX2 = "LC2_A2, LC8_A2, LC7_A2, LC6_A2";
	LC2_A2  : LORAX2 = "LC3_A2, LC2_A2, LC8_A2, LC4_A2";
	LC8_A2  : LORAX2 = "OD0P84, LC3_A2, LC8_A2, LC5_A2";
	LC7_A2  : LORAX2 = "OD0P84, LC7_A2, LC6_A2, LC5_A2";
	LC6_A2  : LORAX2 = "X, X, OD0P84, LC6_A2";
	LC5_A2  : LORAX2 = "LC2_A2, LC8_A2, LC7_A2, LC6_A2";
	LC4_A2  : LORAX2 = "X, X, OD0P84, LC5_A2";
	LC3_A1  : LORAX2 = "X, X, LC1_A1, LC1_A2";
END;