📄 clk_div.rpt
字号:
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 01 DFFE 0 3 0 1 |clk_div4:u1|:3
- 2 - A 01 DFFE 1 2 0 1 |clk_div4:u1|count1 (|clk_div4:u1|:5)
- 4 - A 01 DFFE 1 1 0 2 |clk_div4:u1|count0 (|clk_div4:u1|:6)
- 3 - A 02 AND2 0 2 0 2 |clk_div10:u0|LPM_ADD_SUB:66|addcore:adder|:55
- 1 - A 02 DFFE + 0 4 1 4 |clk_div10:u0|:3
- 2 - A 02 DFFE + 0 3 0 2 |clk_div10:u0|count3 (|clk_div10:u0|:5)
- 8 - A 02 DFFE + 1 2 0 3 |clk_div10:u0|count2 (|clk_div10:u0|:6)
- 7 - A 02 DFFE + 1 2 0 3 |clk_div10:u0|count1 (|clk_div10:u0|:7)
- 6 - A 02 DFFE + 1 0 0 4 |clk_div10:u0|count0 (|clk_div10:u0|:8)
- 5 - A 02 OR2 ! 0 4 0 3 |clk_div10:u0|:33
- 4 - A 02 AND2 s 1 1 0 1 |clk_div10:u0|~92~1
- 3 - A 01 AND2 0 2 1 0 :8
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\work\max+plus_work\stopwatch\clk_div.rpt
clk_div
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\work\max+plus_work\stopwatch\clk_div.rpt
clk_div
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 clk
DFF 5 |clk_div10:u0|:3
Device-Specific Information: d:\work\max+plus_work\stopwatch\clk_div.rpt
clk_div
** EQUATIONS **
clk : INPUT;
sysreset : INPUT;
-- Node name is 'clk0'
-- Equation name is 'clk0', type is output
clk0 = _LC1_A2;
-- Node name is 'clk1'
-- Equation name is 'clk1', type is output
clk1 = _LC3_A1;
-- Node name is '|clk_div4:u1|:6' = '|clk_div4:u1|count0'
-- Equation name is '_LC4_A1', type is buried
_LC4_A1 = DFFE( _EQ001, _LC1_A2, VCC, VCC, VCC);
_EQ001 = !_LC4_A1 & !sysreset;
-- Node name is '|clk_div4:u1|:5' = '|clk_div4:u1|count1'
-- Equation name is '_LC2_A1', type is buried
_LC2_A1 = DFFE( _EQ002, _LC1_A2, VCC, VCC, VCC);
_EQ002 = !_LC2_A1 & _LC4_A1 & !sysreset
# _LC2_A1 & !_LC4_A1 & !sysreset;
-- Node name is '|clk_div4:u1|:3'
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = DFFE( _EQ003, _LC1_A2, VCC, VCC, VCC);
_EQ003 = _LC2_A1 & _LC4_A1;
-- Node name is '|clk_div10:u0|:8' = '|clk_div10:u0|count0'
-- Equation name is '_LC6_A2', type is buried
_LC6_A2 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !_LC6_A2 & !sysreset;
-- Node name is '|clk_div10:u0|:7' = '|clk_div10:u0|count1'
-- Equation name is '_LC7_A2', type is buried
_LC7_A2 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !_LC5_A2 & _LC6_A2 & !_LC7_A2 & !sysreset
# !_LC5_A2 & !_LC6_A2 & _LC7_A2 & !sysreset;
-- Node name is '|clk_div10:u0|:6' = '|clk_div10:u0|count2'
-- Equation name is '_LC8_A2', type is buried
_LC8_A2 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !_LC3_A2 & !_LC5_A2 & _LC8_A2 & !sysreset
# _LC3_A2 & !_LC5_A2 & !_LC8_A2 & !sysreset;
-- Node name is '|clk_div10:u0|:5' = '|clk_div10:u0|count3'
-- Equation name is '_LC2_A2', type is buried
_LC2_A2 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC2_A2 & _LC4_A2 & !_LC8_A2
# _LC2_A2 & !_LC3_A2 & _LC4_A2
# !_LC2_A2 & _LC3_A2 & _LC4_A2 & _LC8_A2;
-- Node name is '|clk_div10:u0|LPM_ADD_SUB:66|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A2', type is buried
_LC3_A2 = LCELL( _EQ008);
_EQ008 = _LC6_A2 & _LC7_A2;
-- Node name is '|clk_div10:u0|:3'
-- Equation name is '_LC1_A2', type is buried
_LC1_A2 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = _LC2_A2 & _LC6_A2 & !_LC7_A2 & !_LC8_A2;
-- Node name is '|clk_div10:u0|:33'
-- Equation name is '_LC5_A2', type is buried
!_LC5_A2 = _LC5_A2~NOT;
_LC5_A2~NOT = LCELL( _EQ010);
_EQ010 = !_LC6_A2
# _LC7_A2
# _LC8_A2
# !_LC2_A2;
-- Node name is '|clk_div10:u0|~92~1'
-- Equation name is '_LC4_A2', type is buried
-- synthesized logic cell
_LC4_A2 = LCELL( _EQ011);
_EQ011 = !_LC5_A2 & !sysreset;
-- Node name is ':8'
-- Equation name is '_LC3_A1', type is buried
_LC3_A1 = LCELL( _EQ012);
_EQ012 = _LC1_A1 & _LC1_A2;
Project Information d:\work\max+plus_work\stopwatch\clk_div.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 9,774K
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