count3.vhd

来自「一个用VHDL编写的秒表程序」· VHDL 代码 · 共 34 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity count3 is
	port(reset	:in std_logic;
		enable	:in std_logic;
		clk		:in std_logic;
		cout	:out std_logic;
		q		:out std_logic_vector(1 downto 0)
		);
end count3;
architecture rtl of count3 is
	signal q_temp	:	std_logic_vector(1 downto 0);
begin
	process(clk)
	begin
		if(clk'event and clk='1')then
			if(reset='1')then
				q_temp<=(others=>'0');
			elsif(enable='1')then
				if(q_temp="10")then
					q_temp<=(others=>'0');
				else
					q_temp<=q_temp+1;
				end if;
			end if;
		end if;
		q<=q_temp;
	end process;
	cout<='1' when q_temp="10" and enable='1' else '0';
end rtl;