time_counter.vhd

一个用VHDL编写的秒表程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity time_counter is
	port(sysreset	:in std_logic;
			reset0	:in std_logic;
			clk0	:in std_logic;
			enable	:in std_logic;
			hr10	:out std_logic_vector(3 downto 0);
			hr		:out std_logic_vector(3 downto 0);
			min10	:out std_logic_vector(2 downto 0);
			min 	:out std_logic_vector(3 downto 0);
            sec10	:out std_logic_vector(2 downto 0);
            sec 	:out std_logic_vector(3 downto 0);
            sec01	:out std_logic_vector(3 downto 0);
            sec001	:out std_logic_vector(3 downto 0)       
			);
end time_counter;
architecture rtl of time_counter is
	component count10
		port(reset	:in std_logic;
			enable	:in std_logic;
			clk		:in std_logic;
			cout	:out std_logic;
			q		:out std_logic_vector(3 downto 0)
			);
	end component;
	
	component count6
		port(reset	:in std_logic;
			enable	:in std_logic;
			clk		:in std_logic;
			cout	:out std_logic;
			q		:out std_logic_vector(2 downto 0)
			);
	end component;
	
	component count4
		port(reset	:in std_logic;
		enable	:in std_logic;
		clk		:in std_logic;
		cout	:out std_logic;
		q		:out std_logic_vector(1 downto 0)
		);
	end component;
	component count3
		port(reset	:in std_logic;
			enable	:in std_logic;
			clk		:in std_logic;
			cout	:out std_logic;
			q		:out std_logic_vector(1 downto 0)
			);
	end component;
	
	signal co1,co2,co3,co4,co5,co6,co7,co8	:std_logic;
	signal reset_temp						:std_logic;
	signal hr_temp,hr10_temp				:std_logic_vector(1 downto 0);

begin
	reset_temp<=sysreset OR reset0;
	u0:count10
		port map(reset_temp,enable,clk0,co1,sec001);
	u1:count10
		port map(reset_temp,co1,clk0,co2,sec01);
	u2:count10
		port map(reset_temp,co2,clk0,co3,sec);
	u3:count6
		port map(reset_temp,co3,clk0,co4,sec10);
	u4:count10
		port map(reset_temp,co4,clk0,co5,min);
	u5:count6
		port map(reset_temp,co5,clk0,co6,min10);
	u6:count4
		port map(reset_temp,co6,clk0,co7,hr_temp);
	u7:count3
		port map(reset_temp,co7,clk0,co8,hr10_temp);
	hr<="0000"when hr10_temp="00" and hr_temp="00" else
		"0001"when hr10_temp="00" and hr_temp="01" else
		"0010"when hr10_temp="00" and hr_temp="10" else
		"0011"when hr10_temp="00" and hr_temp="11" else
		"0100"when hr10_temp="01" and hr_temp="00" else
		"0101"when hr10_temp="01" and hr_temp="01" else
		"0110"when hr10_temp="01" and hr_temp="10" else
		"0111"when hr10_temp="01" and hr_temp="11" else
		"1000"when hr10_temp="10" and hr_temp="00" else
		"1001"when hr10_temp="10" and hr_temp="01" else
		"0000"when hr10_temp="10" and hr_temp="10" else
		"0001";
	hr10<="0001"when (hr10_temp="10" and hr_temp="10") OR (hr10_temp="10" and hr_temp="11") else "0000";
end rtl;