seg7.vhd

来自「一个用VHDL编写的秒表程序」· VHDL 代码 · 共 41 行

library ieee;
use ieee.std_logic_1164.all;

entity seg7 is
	port(q	:in std_logic_vector(3 downto 0);
		segment:out std_logic_vector(6 downto 0)
		);
end seg7;

architecture rtl of seg7 is
begin
	process(q)
	begin
		case q is
			when"0000"=>segment<="0111111";
			when"0001"=>segment<="0000110";
			when"0010"=>segment<="1011011";
			when"0011"=>segment<="1001111";
			when"0100"=>segment<="1100110";
			when"0101"=>segment<="1101101";
			when"0110"=>segment<="1111101";
			when"0111"=>segment<="0100111";
			when"1000"=>segment<="1111111";
			when"1001"=>segment<="1101111";
			when others =>segment<="1111001";
		end case;
	end process;
end rtl;