time_choose.vhd

一个用VHDL编写的秒表程序

library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_unsigned.all;
--use ieee.std_logic_arith.all;

entity time_choose is
	port(sel	:in std_logic_vector(2 downto 0);		
		hr10	:in std_logic_vector(3 downto 0);
		hr		:in std_logic_vector(3 downto 0);
		min10	:in std_logic_vector(2 downto 0);
		min		:in std_logic_vector(3 downto 0);
		sec10	:in std_logic_vector(2 downto 0);
		sec		:in std_logic_vector(3 downto 0);
		sec01	:in std_logic_vector(3 downto 0);
		sec001	:in std_logic_vector(3 downto 0);
		q		:out std_logic_vector(3 downto 0)
		);
end time_choose;

architecture rtl of time_choose is
begin
	process(sel,hr10,hr,min10,min,sec10,sec,sec01,sec001)
	begin
		case sel is
			when"000"=>q<=sec001;
			when"001"=>q<=sec01;
			when"010"=>q<=sec;
			when"011"=>q<='0'&sec10;
			when"100"=>q<=min;
			when"101"=>q<='0'&min10;
			when"110"=>q<=hr;
			when"111"=>q<=hr10;
			when others =>q<="XXXX";
		end case;
	end process;
end rtl;