clk_div4.vhd

来自「一个用VHDL编写的秒表程序」· VHDL 代码 · 共 41 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity clk_div4 is
	port(clk :in std_logic;
		reset:in std_logic;
		clk_div:out std_logic
		);
	end clk_div4;

architecture rtl of clk_div4 is
	signal count:std_logic_vector(1 downto 0);
begin
	process(clk)
	begin
		if(clk'event and clk='1')then
			if(reset='1')then
				count<=(others=>'0');
			elsif(count="11")then
				count<=(others=>'0');
			else
				count<=count+1;
			end if;
		end if;
	end process;

	process(clk)
	begin
		if(clk'event and clk='1')then
			if(count="11")then
				clk_div<='1';
			else
				clk_div<='0';
			end if;
		end if;
	end process;
end rtl;