choose_decode.vhd

来自「一个用VHDL编写的秒表程序」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;

entity choose_decode is
	port(sel	:in std_logic_vector(2 downto 0);
		choose	:out std_logic_vector(7 downto 0)
		);
end choose_decode;
architecture rtl of choose_decode is
begin
	process(sel)
	begin
		case sel is
			when"000"=>choose<="00000001";
			when"001"=>choose<="00000010";
			when"010"=>choose<="00000100";
			when"011"=>choose<="00001000";
			when"100"=>choose<="00010000";
			when"101"=>choose<="00100000";
			when"110"=>choose<="01000000";
			when"111"=>choose<="10000000";
			when others=>choose<="XXXXXXXX";	
		end case;						
	end process;
end rtl;