📄 time_counter.rpt
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-- Equation name is '_LC5_C5', type is buried
_LC5_C5 = LCELL( _EQ037);
_EQ037 = _LC1_C5 & _LC3_C8 & !_LC7_C5
# _LC1_C5 & _LC3_C8 & !_LC3_C12
# !_LC1_C5 & _LC3_C8 & _LC3_C12 & _LC7_C5;
-- Node name is '|count10:u1|:151'
-- Equation name is '_LC2_C5', type is buried
_LC2_C5 = LCELL( _EQ038);
_EQ038 = _LC3_C8 & !_LC3_C12 & _LC7_C5
# _LC3_C8 & _LC3_C12 & !_LC7_C5;
-- Node name is '|count10:u1|:227'
-- Equation name is '_LC1_C8', type is buried
_LC1_C8 = LCELL( _EQ039);
_EQ039 = _LC1_C6 & _LC5_C8;
-- Node name is '|count10:u2|LPM_ADD_SUB:77|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_A4', type is buried
_LC8_A4 = LCELL( _EQ040);
_EQ040 = _LC3_A11 & _LC5_A4;
-- Node name is '|count10:u2|:12' = '|count10:u2|q_temp0'
-- Equation name is '_LC3_A11', type is buried
_LC3_A11 = DFFE( _EQ041, GLOBAL( clk0), VCC, VCC, VCC);
_EQ041 = !_LC1_B10 & !_LC1_C8 & _LC3_A11
# !_LC1_B10 & _LC1_C8 & !_LC3_A11;
-- Node name is '|count10:u2|:11' = '|count10:u2|q_temp1'
-- Equation name is '_LC5_A4', type is buried
_LC5_A4 = DFFE( _EQ042, GLOBAL( clk0), VCC, VCC, VCC);
_EQ042 = !_LC1_B10 & !_LC1_C8 & _LC5_A4
# !_LC1_B10 & _LC6_A4;
-- Node name is '|count10:u2|:10' = '|count10:u2|q_temp2'
-- Equation name is '_LC7_A4', type is buried
_LC7_A4 = DFFE( _EQ043, GLOBAL( clk0), VCC, VCC, VCC);
_EQ043 = !_LC1_B10 & _LC4_A4
# !_LC1_B10 & !_LC1_C8 & _LC7_A4;
-- Node name is '|count10:u2|:9' = '|count10:u2|q_temp3'
-- Equation name is '_LC3_A4', type is buried
_LC3_A4 = DFFE( _EQ044, GLOBAL( clk0), VCC, VCC, VCC);
_EQ044 = !_LC1_B10 & !_LC1_C8 & _LC3_A4
# !_LC1_B10 & _LC2_A4;
-- Node name is '|count10:u2|:52'
-- Equation name is '_LC1_A10', type is buried
_LC1_A10 = LCELL( _EQ045);
_EQ045 = _LC3_A4 & _LC3_A11 & !_LC5_A4 & !_LC7_A4;
-- Node name is '|count10:u2|~130~1'
-- Equation name is '_LC1_A4', type is buried
-- synthesized logic cell
_LC1_A4 = LCELL( _EQ046);
_EQ046 = !_LC1_A10 & _LC1_C8;
-- Node name is '|count10:u2|:130'
-- Equation name is '_LC2_A4', type is buried
_LC2_A4 = LCELL( _EQ047);
_EQ047 = _LC1_A4 & _LC3_A4 & !_LC8_A4
# _LC1_A4 & _LC3_A4 & !_LC7_A4
# _LC1_A4 & !_LC3_A4 & _LC7_A4 & _LC8_A4;
-- Node name is '|count10:u2|:142'
-- Equation name is '_LC4_A4', type is buried
_LC4_A4 = LCELL( _EQ048);
_EQ048 = _LC1_A4 & !_LC5_A4 & _LC7_A4
# _LC1_A4 & !_LC3_A11 & _LC7_A4
# _LC1_A4 & _LC3_A11 & _LC5_A4 & !_LC7_A4;
-- Node name is '|count10:u2|:151'
-- Equation name is '_LC6_A4', type is buried
_LC6_A4 = LCELL( _EQ049);
_EQ049 = _LC1_A4 & !_LC3_A11 & _LC5_A4
# _LC1_A4 & _LC3_A11 & !_LC5_A4;
-- Node name is '|count10:u2|:227'
-- Equation name is '_LC7_A2', type is buried
_LC7_A2 = LCELL( _EQ050);
_EQ050 = _LC1_A10 & _LC1_C8;
-- Node name is '|count10:u4|LPM_ADD_SUB:77|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B9', type is buried
_LC4_B9 = LCELL( _EQ051);
_EQ051 = _LC2_B12 & _LC6_B7;
-- Node name is '|count10:u4|:12' = '|count10:u4|q_temp0'
-- Equation name is '_LC2_B12', type is buried
_LC2_B12 = DFFE( _EQ052, GLOBAL( clk0), VCC, VCC, VCC);
_EQ052 = !_LC1_A2 & !_LC1_B10 & _LC2_B12
# _LC1_A2 & !_LC1_B10 & !_LC2_B12;
-- Node name is '|count10:u4|:11' = '|count10:u4|q_temp1'
-- Equation name is '_LC6_B7', type is buried
_LC6_B7 = DFFE( _EQ053, GLOBAL( clk0), VCC, VCC, VCC);
_EQ053 = _LC1_B7 & !_LC1_B10
# !_LC1_A2 & !_LC1_B10 & _LC6_B7;
-- Node name is '|count10:u4|:10' = '|count10:u4|q_temp2'
-- Equation name is '_LC4_B7', type is buried
_LC4_B7 = DFFE( _EQ054, GLOBAL( clk0), VCC, VCC, VCC);
_EQ054 = !_LC1_B10 & _LC2_B7
# !_LC1_A2 & !_LC1_B10 & _LC4_B7;
-- Node name is '|count10:u4|:9' = '|count10:u4|q_temp3'
-- Equation name is '_LC1_B9', type is buried
_LC1_B9 = DFFE( _EQ055, GLOBAL( clk0), VCC, VCC, VCC);
_EQ055 = !_LC1_B10 & _LC6_B9
# !_LC1_A2 & _LC1_B9 & !_LC1_B10;
-- Node name is '|count10:u4|:52'
-- Equation name is '_LC5_B9', type is buried
_LC5_B9 = LCELL( _EQ056);
_EQ056 = _LC1_B9 & _LC2_B12 & !_LC4_B7 & !_LC6_B7;
-- Node name is '|count10:u4|~130~1'
-- Equation name is '_LC3_B9', type is buried
-- synthesized logic cell
_LC3_B9 = LCELL( _EQ057);
_EQ057 = _LC1_A2 & !_LC5_B9;
-- Node name is '|count10:u4|:130'
-- Equation name is '_LC6_B9', type is buried
_LC6_B9 = LCELL( _EQ058);
_EQ058 = _LC1_B9 & _LC3_B9 & !_LC4_B9
# _LC1_B9 & _LC3_B9 & !_LC4_B7
# !_LC1_B9 & _LC3_B9 & _LC4_B7 & _LC4_B9;
-- Node name is '|count10:u4|:142'
-- Equation name is '_LC2_B7', type is buried
_LC2_B7 = LCELL( _EQ059);
_EQ059 = _LC3_B9 & _LC4_B7 & !_LC6_B7
# !_LC2_B12 & _LC3_B9 & _LC4_B7
# _LC2_B12 & _LC3_B9 & !_LC4_B7 & _LC6_B7;
-- Node name is '|count10:u4|:151'
-- Equation name is '_LC1_B7', type is buried
_LC1_B7 = LCELL( _EQ060);
_EQ060 = !_LC2_B12 & _LC3_B9 & _LC6_B7
# _LC2_B12 & _LC3_B9 & !_LC6_B7;
-- Node name is '|count10:u4|:227'
-- Equation name is '_LC2_B9', type is buried
_LC2_B9 = LCELL( _EQ061);
_EQ061 = _LC1_A2 & _LC5_B9;
-- Node name is ':48'
-- Equation name is '_LC1_B10', type is buried
!_LC1_B10 = _LC1_B10~NOT;
_LC1_B10~NOT = LCELL( _EQ062);
_EQ062 = !reset0 & !sysreset;
-- Node name is ':230'
-- Equation name is '_LC8_B1', type is buried
_LC8_B1 = LCELL( _EQ063);
_EQ063 = _LC2_B1 & !_LC2_B8 & !_LC4_B1;
-- Node name is ':266'
-- Equation name is '_LC1_B1', type is buried
_LC1_B1 = LCELL( _EQ064);
_EQ064 = !_LC2_B1 & _LC4_B1;
-- Node name is ':302'
-- Equation name is '_LC3_B1', type is buried
_LC3_B1 = LCELL( _EQ065);
_EQ065 = !_LC2_B1 & _LC2_B8;
-- Node name is ':338'
-- Equation name is '_LC5_B1', type is buried
_LC5_B1 = LCELL( _EQ066);
_EQ066 = _LC1_B11
# _LC2_B1 & _LC4_B1;
-- Node name is '~360~1'
-- Equation name is '~360~1', location is LC7_B1, type is buried.
-- synthesized logic cell
_LC7_B1 = LCELL( _EQ067);
_EQ067 = _LC2_B1 & _LC2_B8 & !_LC4_B1;
Project Information d:\work\max+plus_work\stopwatch\time_counter.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,439K
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