📄 time_counter.rpt
字号:
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\work\max+plus_work\stopwatch\time_counter.rpt
time_counter
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
65 - - B -- OUTPUT 0 1 0 0 hr0
66 - - B -- OUTPUT 0 1 0 0 hr1
21 - - B -- OUTPUT 0 1 0 0 hr2
25 - - B -- OUTPUT 0 1 0 0 hr3
64 - - B -- OUTPUT 0 1 0 0 hr100
62 - - C -- OUTPUT 0 0 0 0 hr101
69 - - A -- OUTPUT 0 0 0 0 hr102
73 - - A -- OUTPUT 0 0 0 0 hr103
22 - - B -- OUTPUT 0 1 0 0 min0
24 - - B -- OUTPUT 0 1 0 0 min1
23 - - B -- OUTPUT 0 1 0 0 min2
67 - - B -- OUTPUT 0 1 0 0 min3
7 - - - 03 OUTPUT 0 1 0 0 min100
6 - - - 04 OUTPUT 0 1 0 0 min101
8 - - - 03 OUTPUT 0 1 0 0 min102
17 - - A -- OUTPUT 0 1 0 0 sec0
18 - - A -- OUTPUT 0 1 0 0 sec1
19 - - A -- OUTPUT 0 1 0 0 sec2
72 - - A -- OUTPUT 0 1 0 0 sec3
29 - - C -- OUTPUT 0 1 0 0 sec0010
28 - - C -- OUTPUT 0 1 0 0 sec010
61 - - C -- OUTPUT 0 1 0 0 sec0011
30 - - C -- OUTPUT 0 1 0 0 sec011
59 - - C -- OUTPUT 0 1 0 0 sec0012
27 - - C -- OUTPUT 0 1 0 0 sec012
58 - - C -- OUTPUT 0 1 0 0 sec0013
60 - - C -- OUTPUT 0 1 0 0 sec013
16 - - A -- OUTPUT 0 1 0 0 sec100
70 - - A -- OUTPUT 0 1 0 0 sec101
71 - - A -- OUTPUT 0 1 0 0 sec102
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\work\max+plus_work\stopwatch\time_counter.rpt
time_counter
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - B 01 DFFE + 0 3 0 6 |count3:u7|q_temp1 (|count3:u7|:7)
- 4 - B 01 DFFE + 0 3 0 5 |count3:u7|q_temp0 (|count3:u7|:8)
- 2 - B 08 DFFE + 0 3 0 4 |count4:u6|q_temp1 (|count4:u6|:7)
- 1 - B 11 DFFE + 0 2 0 3 |count4:u6|q_temp0 (|count4:u6|:8)
- 6 - B 01 AND2 0 3 0 2 |count4:u6|:133
- 3 - A 02 DFFE + 0 2 1 3 |count6:u3|q_temp2 (|count6:u3|:8)
- 5 - A 02 DFFE + 0 2 1 3 |count6:u3|q_temp1 (|count6:u3|:9)
- 4 - A 02 DFFE + 0 2 1 3 |count6:u3|q_temp0 (|count6:u3|:10)
- 2 - A 02 OR2 0 4 0 1 |count6:u3|:104
- 6 - A 02 OR2 0 4 0 1 |count6:u3|:116
- 1 - A 02 AND2 0 4 0 6 |count6:u3|:180
- 2 - B 03 DFFE + 2 1 1 3 |count6:u5|q_temp2 (|count6:u5|:8)
- 3 - B 03 DFFE + 2 1 1 3 |count6:u5|q_temp1 (|count6:u5|:9)
- 4 - B 03 DFFE + 2 1 1 3 |count6:u5|q_temp0 (|count6:u5|:10)
- 5 - B 03 OR2 0 4 0 1 |count6:u5|:104
- 6 - B 03 OR2 0 4 0 1 |count6:u5|:116
- 1 - B 03 AND2 0 4 0 3 |count6:u5|:180
- 3 - C 06 AND2 0 2 0 1 |count10:u0|LPM_ADD_SUB:77|addcore:adder|:55
- 7 - C 06 DFFE + 1 2 1 2 |count10:u0|q_temp3 (|count10:u0|:9)
- 5 - C 06 DFFE + 1 2 1 3 |count10:u0|q_temp2 (|count10:u0|:10)
- 3 - C 05 DFFE + 1 2 1 4 |count10:u0|q_temp1 (|count10:u0|:11)
- 5 - C 11 DFFE + 1 1 1 4 |count10:u0|q_temp0 (|count10:u0|:12)
- 4 - C 06 AND2 0 4 0 2 |count10:u0|:52
- 2 - C 06 AND2 s 1 1 0 3 |count10:u0|~130~1
- 6 - C 06 OR2 0 4 0 1 |count10:u0|:130
- 8 - C 06 OR2 0 4 0 1 |count10:u0|:142
- 4 - C 05 OR2 0 3 0 1 |count10:u0|:151
- 1 - C 06 AND2 1 1 0 6 |count10:u0|:227
- 2 - C 08 AND2 0 2 0 1 |count10:u1|LPM_ADD_SUB:77|addcore:adder|:55
- 4 - C 08 DFFE + 0 3 1 2 |count10:u1|q_temp3 (|count10:u1|:9)
- 1 - C 05 DFFE + 0 3 1 3 |count10:u1|q_temp2 (|count10:u1|:10)
- 7 - C 05 DFFE + 0 3 1 4 |count10:u1|q_temp1 (|count10:u1|:11)
- 3 - C 12 DFFE + 0 2 1 4 |count10:u1|q_temp0 (|count10:u1|:12)
- 5 - C 08 AND2 0 4 0 2 |count10:u1|:52
- 3 - C 08 AND2 s 0 2 0 3 |count10:u1|~130~1
- 6 - C 08 OR2 0 4 0 1 |count10:u1|:130
- 5 - C 05 OR2 0 4 0 1 |count10:u1|:142
- 2 - C 05 OR2 0 3 0 1 |count10:u1|:151
- 1 - C 08 AND2 0 2 0 6 |count10:u1|:227
- 8 - A 04 AND2 0 2 0 1 |count10:u2|LPM_ADD_SUB:77|addcore:adder|:55
- 3 - A 04 DFFE + 0 3 1 2 |count10:u2|q_temp3 (|count10:u2|:9)
- 7 - A 04 DFFE + 0 3 1 3 |count10:u2|q_temp2 (|count10:u2|:10)
- 5 - A 04 DFFE + 0 3 1 4 |count10:u2|q_temp1 (|count10:u2|:11)
- 3 - A 11 DFFE + 0 2 1 4 |count10:u2|q_temp0 (|count10:u2|:12)
- 1 - A 10 AND2 0 4 0 2 |count10:u2|:52
- 1 - A 04 AND2 s 0 2 0 3 |count10:u2|~130~1
- 2 - A 04 OR2 0 4 0 1 |count10:u2|:130
- 4 - A 04 OR2 0 4 0 1 |count10:u2|:142
- 6 - A 04 OR2 0 3 0 1 |count10:u2|:151
- 7 - A 02 AND2 0 2 0 4 |count10:u2|:227
- 4 - B 09 AND2 0 2 0 1 |count10:u4|LPM_ADD_SUB:77|addcore:adder|:55
- 1 - B 09 DFFE + 0 3 1 2 |count10:u4|q_temp3 (|count10:u4|:9)
- 4 - B 07 DFFE + 0 3 1 3 |count10:u4|q_temp2 (|count10:u4|:10)
- 6 - B 07 DFFE + 0 3 1 4 |count10:u4|q_temp1 (|count10:u4|:11)
- 2 - B 12 DFFE + 0 2 1 4 |count10:u4|q_temp0 (|count10:u4|:12)
- 5 - B 09 AND2 0 4 0 2 |count10:u4|:52
- 3 - B 09 AND2 s 0 2 0 3 |count10:u4|~130~1
- 6 - B 09 OR2 0 4 0 1 |count10:u4|:130
- 2 - B 07 OR2 0 4 0 1 |count10:u4|:142
- 1 - B 07 OR2 0 3 0 1 |count10:u4|:151
- 2 - B 09 AND2 0 2 0 4 |count10:u4|:227
- 1 - B 10 AND2 ! 2 0 0 23 :48
- 8 - B 01 AND2 0 3 1 0 :230
- 1 - B 01 AND2 0 2 1 0 :266
- 3 - B 01 AND2 0 2 1 0 :302
- 5 - B 01 OR2 0 3 1 0 :338
- 7 - B 01 AND2 s 0 3 1 0 ~360~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\work\max+plus_work\stopwatch\time_counter.rpt
time_counter
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/ 96( 3%) 8/ 48( 16%) 0/ 48( 0%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
B: 4/ 96( 4%) 12/ 48( 25%) 0/ 48( 0%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 4/ 96( 4%) 9/ 48( 18%) 0/ 48( 0%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\work\max+plus_work\stopwatch\time_counter.rpt
time_counter
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 26 clk0
Device-Specific Information: d:\work\max+plus_work\stopwatch\time_counter.rpt
time_counter
** EQUATIONS **
clk0 : INPUT;
enable : INPUT;
reset0 : INPUT;
sysreset : INPUT;
-- Node name is 'hr0'
-- Equation name is 'hr0', type is output
hr0 = _LC5_B1;
-- Node name is 'hr1'
-- Equation name is 'hr1', type is output
hr1 = _LC3_B1;
-- Node name is 'hr2'
-- Equation name is 'hr2', type is output
hr2 = _LC1_B1;
-- Node name is 'hr3'
-- Equation name is 'hr3', type is output
hr3 = _LC8_B1;
-- Node name is 'hr100'
-- Equation name is 'hr100', type is output
hr100 = _LC7_B1;
-- Node name is 'hr101'
-- Equation name is 'hr101', type is output
hr101 = GND;
-- Node name is 'hr102'
-- Equation name is 'hr102', type is output
hr102 = GND;
-- Node name is 'hr103'
-- Equation name is 'hr103', type is output
hr103 = GND;
-- Node name is 'min0'
-- Equation name is 'min0', type is output
min0 = _LC2_B12;
-- Node name is 'min1'
-- Equation name is 'min1', type is output
min1 = _LC6_B7;
-- Node name is 'min2'
-- Equation name is 'min2', type is output
min2 = _LC4_B7;
-- Node name is 'min3'
-- Equation name is 'min3', type is output
min3 = _LC1_B9;
-- Node name is 'min100'
-- Equation name is 'min100', type is output
min100 = _LC4_B3;
-- Node name is 'min101'
-- Equation name is 'min101', type is output
min101 = _LC3_B3;
-- Node name is 'min102'
-- Equation name is 'min102', type is output
min102 = _LC2_B3;
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