core.tpl

8051VHDL原代码

[COREGEN.VERILOG Component Instantiation.mc8051_ram]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="mc8051_ram YourInstanceName ("
text007="    .addr(addr),"
text008="    .clk(clk),"
text009="    .din(din),"
text010="    .dout(dout),"
text011="    .en(en),"
text012="    .we(we));"
text013=""
text014=" "
type=template
[COREGEN.VERILOG Component Instantiation.mc8051_rom]
text000=" "
text001=" "
text002="// The following must be inserted into your Verilog file for this"
text003="// core to be instantiated. Change the instance name and port connections"
text004="// (in parentheses) to your own signal names."
text005=" "
text006="mc8051_rom YourInstanceName ("
text007="    .addr(addr),"
text008="    .clk(clk),"
text009="    .dout(dout));"
text010=""
text011=" "
type=template
[COREGEN.VHDL Component Instantiation.mc8051_ram]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component mc8051_ram"
text005="    port ("
text006="    addr: IN std_logic_VECTOR(6 downto 0);"
text007="    clk: IN std_logic;"
text008="    din: IN std_logic_VECTOR(7 downto 0);"
text009="    dout: OUT std_logic_VECTOR(7 downto 0);"
text010="    en: IN std_logic;"
text011="    we: IN std_logic);"
text012="end component;"
text013=""
text014=""
text015=""
text016=" "
text017="-------------------------------------------------------------"
text018=" "
text019="-- The following code must appear in the VHDL architecture body."
text020="-- Substitute your own instance name and net names."
text021=" "
text022="your_instance_name : mc8051_ram"
text023="        port map ("
text024="            addr => addr,"
text025="            clk => clk,"
text026="            din => din,"
text027="            dout => dout,"
text028="            en => en,"
text029="            we => we);"
text030=" "
type=template
[COREGEN.VHDL Component Instantiation.mc8051_rom]
text000=" "
text001=" "
text002="-- The following code must appear in the VHDL architecture header:"
text003=" "
text004="component mc8051_rom"
text005="    port ("
text006="    addr: IN std_logic_VECTOR(9 downto 0);"
text007="    clk: IN std_logic;"
text008="    dout: OUT std_logic_VECTOR(7 downto 0));"
text009="end component;"
text010=""
text011=""
text012=""
text013=" "
text014="-------------------------------------------------------------"
text015=" "
text016="-- The following code must appear in the VHDL architecture body."
text017="-- Substitute your own instance name and net names."
text018=" "
text019="your_instance_name : mc8051_rom"
text020="        port map ("
text021="            addr => addr,"
text022="            clk => clk,"
text023="            dout => dout);"
text024=" "
type=template