__projnav.log

8051VHDL原代码

Mapping completed.
See MAP report file "mc8051_top_map.mrp" for details.




Started process "Place & Route".




Constraints file: mc8051_top.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
D:/Xilinx.
   "mc8051_top" is an NCD, version 3.1, device xc3s200, package ft256, speed -5

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "ADVANCED 1.35 2005-01-22".


Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs            10 out of 74     13%

   Number of MULT18X18s                1 out of 12      8%
   Number of RAMB16s                   2 out of 12     16%
   Number of Slices                 1583 out of 1920   82%
      Number of SLICEMs               50 out of 960     5%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98f106) REAL time: 3 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 3 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 3 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 3 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 3 secs 

Phase 6.8
.........................................
Phase 6.8 (Checksum:d378e9) REAL time: 10 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 10 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 13 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 13 secs 

Writing design to file mc8051_top.ncd


Total REAL time to Placer completion: 13 secs 
Total CPU time to Placer completion: 13 secs 

Starting Router

Phase 1: 11146 unrouted;       REAL time: 14 secs 

Phase 2: 10685 unrouted;       REAL time: 14 secs 

Phase 3: 5832 unrouted;       REAL time: 16 secs 

Phase 4: 0 unrouted;       REAL time: 24 secs 


Total REAL time to Router completion: 24 secs 
Total CPU time to Router completion: 24 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           s_clk_pre |      BUFGMUX5| No   |  396 |  0.004     |  0.884      |
+---------------------+--------------+------+------+------------+-------------+
|               clk_c |      BUFGMUX0| No   |    3 |  0.000     |  0.880      |
+---------------------+--------------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 26 secs 
Total CPU time to PAR completion: 26 secs 

Peak Memory Usage:  97 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file mc8051_top.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
D:/Xilinx.
   "mc8051_top" is an NCD, version 3.1, device xc3s200, package ft256, speed -5

Analysis completed Tue Jun 05 16:24:34 2007
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 14 secs 







Started process "Generate Programming File".



Project Navigator Auto-Make Log File
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Started process "Generate Programming File".



Project Navigator Auto-Make Log File
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Started process "Synthesize".



Project Navigator Auto-Make Log File
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Started process "Synthesize".



Project Navigator Auto-Make Log File
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Started process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\vhdl\f8051/_ngo -uc myucf.ucf -p
xc3s200-ft256-5 mc8051_top.edn mc8051_top.ngd 

Executing edif2ngd -quiet "mc8051_top.edn" "e:\vhdl\f8051\_ngo\mc8051_top.ngo"
Release 7.1i - edif2ngd H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
Reading NGO file 'e:/vhdl/f8051/_ngo/mc8051_top.ngo' ...
Reading module "mc8051_rom.ngo" ( "mc8051_rom.ngo" unchanged since last run )...
Loading design module "e:\vhdl\f8051\_ngo\mc8051_rom.ngo"...
Reading module "mc8051_ram.ngo" ( "mc8051_ram.ngo" unchanged since last run )...
Loading design module "e:\vhdl\f8051\_ngo\mc8051_ram.ngo"...

Applying constraints in "myucf.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "mc8051_top.ngd" ...

Writing NGDBUILD log file "mc8051_top.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s200ft256-5".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Number of Slice Flip Flops:         590 out of   3,840   15%
  Number of 4 input LUTs:           2,730 out of   3,840   71%
Logic Distribution:
  Number of occupied Slices:                        1,583 out of   1,920   82%
    Number of Slices containing only related logic:   1,583 out of   1,583  100%
    Number of Slices containing unrelated logic:          0 out of   1,583    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          2,791 out of   3,840   72%
  Number used as logic:              2,730
  Number used as a route-thru:          45
  Number used for Dual Port RAMs:       16
    (Two LUTs used per Dual Port RAM)
  Number of bonded IOBs:               74 out of     173   42%
  Number of Block RAMs:                2 out of      12   16%
  Number of MULT18X18s:                1 out of      12    8%
  Number of GCLKs:                     2 out of       8   25%

Total equivalent gate count for design:  159,259
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  129 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "mc8051_top_map.mrp" for details.




Started process "Place & Route".




Constraints file: mc8051_top.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
D:/Xilinx.
   "mc8051_top" is an NCD, version 3.1, device xc3s200, package ft256, speed -5

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "ADVANCED 1.35 2005-01-22".


Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs            10 out of 74     13%

   Number of MULT18X18s                1 out of 12      8%
   Number of RAMB16s                   2 out of 12     16%
   Number of Slices                 1583 out of 1920   82%
      Number of SLICEMs               50 out of 960     5%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98f106) REAL time: 4 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 4 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 4 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 4 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 4 secs 

Phase 6.8
.........................................
Phase 6.8 (Checksum:d378e9) REAL time: 12 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 12 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 16 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 16 secs 

Writing design to file mc8051_top.ncd


Total REAL time to Placer completion: 17 secs 
Total CPU time to Placer completion: 14 secs 

Starting Router

Phase 1: 11146 unrouted;       REAL time: 17 secs 

Phase 2: 10685 unrouted;       REAL time: 18 secs 

Phase 3: 5832 unrouted;       REAL time: 20 secs 

Phase 4: 0 unrouted;       REAL time: 32 secs 


Total REAL time to Router completion: 32 secs 
Total CPU time to Router completion: 26 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           s_clk_pre |      BUFGMUX5| No   |  396 |  0.004     |  0.884      |
+---------------------+--------------+------+------+------------+-------------+
|               clk_c |      BUFGMUX0| No   |    3 |  0.000     |  0.880      |
+---------------------+--------------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 36 secs 
Total CPU time to PAR completion: 28 secs 

Peak Memory Usage:  97 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file mc8051_top.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
D:/Xilinx.
   "mc8051_top" is an NCD, version 3.1, device xc3s200, package ft256, speed -5

Analysis completed Thu Oct 25 20:46:47 2007
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 16 secs 







Started process "Generate Programming File".



Project Navigator Auto-Make Log File
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Started process "Synthesize".

Error running Program:
License checkout: synplifypro

Starting:    d:\Program Files\Synplicity\fpga_81\bin\mbin\synplify.exe
Install:     d:\Program Files\Synplicity\fpga_81
Date:        Tue Oct 30 14:47:16 2007
Version:     8.1

Version 8.1

Arguments:   -pro -batch -splash -launchmode mc8051_tmrctr.prj -tcl mc8051_tmrctr_map.tcl
ProductType: synplify_pro

License: synplifypro node-locked 
Running in Xilinx Mode



At line 1 while processing "E:\vhdl\f8051\mc8051_tmrctr.prj"
invalid command name "vhdl"


Error: Project load failed.

exit status=7


Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
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