__projnav.log

8051VHDL原代码

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deleting "mc8051_top_summary.html"
deleting "__projnav/f8051.gfl"
deleting f8051.dhp
Finished cleaning up project


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Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/vhdl/f8051/mc8051_clockdiv.vhd" in Library work.
Entity <mc8051_clockdiv> compiled.
Entity <mc8051_clockdiv> (Architecture <Behavioral>) compiled.


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Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/vhdl/f8051/mc8051_p.vhd" in Library work.
Package <mc8051_p> compiled.
Compiling vhdl file "E:/vhdl/f8051/addsub_ovcy.vhd" in Library work.
Entity <addsub_ovcy> compiled.
Entity <addsub_ovcy> (Architecture <rtl>) compiled.
Compiling vhdl file "E:/vhdl/f8051/addsub_cy.vhd" in Library work.
Entity <addsub_cy> compiled.
Entity <addsub_cy> (Architecture <rtl>) compiled.
Compiling vhdl file "E:/vhdl/f8051/alumux.vhd" in Library work.
Entity <alumux> compiled.
Entity <alumux> (Architecture <rtl>) compiled.
Compiling vhdl file "E:/vhdl/f8051/alucore.vhd" in Library work.
Entity <alucore> compiled.
Entity <alucore> (Architecture <rtl>) compiled.
Compiling vhdl file "E:/vhdl/f8051/addsub_core.vhd" in Library work.
Entity <addsub_core> compiled.
Entity <addsub_core> (Architecture <struc>) compiled.
Compiling vhdl file "E:/vhdl/f8051/comb_mltplr.vhd" in Library work.
Entity <comb_mltplr> compiled.
Entity <comb_mltplr> (Architecture <rtl>) compiled.
Compiling vhdl file "E:/vhdl/f8051/comb_divider.vhd" in Library work.
Entity <comb_divider> compiled.
Entity <comb_divider> (Architecture <rtl>) compiled.
Compiling vhdl file "E:/vhdl/f8051/dcml_adjust.vhd" in Library work.
Entity <dcml_adjust> compiled.
Entity <dcml_adjust> (Architecture <rtl>) compiled.
Compiling vhdl file "E:/vhdl/f8051/mc8051_alu.vhd" in Library work.
Entity <mc8051_alu> compiled.
Entity <mc8051_alu> (Architecture <struc>) compiled.


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Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/vhdl/f8051/mc8051_p.vhd" in Library work.
Compiling vhdl file "E:/vhdl/f8051/control_fsm.vhd" in Library work.
Entity <control_fsm> compiled.
Entity <control_fsm> (Architecture <rtl>) compiled.
Compiling vhdl file "E:/vhdl/f8051/control_mem.vhd" in Library work.
Entity <control_mem> compiled.
Entity <control_mem> (Architecture <rtl>) compiled.
Compiling vhdl file "E:/vhdl/f8051/mc8051_control.vhd" in Library work.
Entity <mc8051_control> compiled.
Entity <mc8051_control> (Architecture <struc>) compiled.


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Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/vhdl/f8051/mc8051_siu.vhd" in Library work.
Entity <mc8051_siu> compiled.
Entity <mc8051_siu> (Architecture <rtl>) compiled.


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Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/vhdl/f8051/mc8051_tmrctr.vhd" in Library work.
Entity <mc8051_tmrctr> compiled.
Entity <mc8051_tmrctr> (Architecture <rtl>) compiled.


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deleting "mc8051_clockdiv.lso"
deleting "mc8051_clockdiv.stx"
deleting "mc8051_alu.lso"
deleting "mc8051_alu.stx"
deleting "mc8051_control.lso"
deleting "mc8051_control.stx"
deleting "mc8051_siu.lso"
deleting "mc8051_siu.stx"
deleting "mc8051_tmrctr.lso"
deleting "mc8051_tmrctr.stx"
deleting "__projnav/f8051.gfl"
Finished cleaning up project


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Started process "Synthesize".



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Started process "Synthesize".





Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\vhdl\f8051/_ngo -nt timestamp -i -p
xc3s200-ft256-5 mc8051_top.edn mc8051_top.ngd 

Executing edif2ngd -quiet "mc8051_top.edn" "e:\vhdl\f8051\_ngo\mc8051_top.ngo"
Release 7.1.04i - edif2ngd H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
Reading NGO file 'e:/vhdl/f8051/_ngo/mc8051_top.ngo' ...
Executing edif2ngd -noa "mc8051_rom.edn" "e:\vhdl\f8051\_ngo\mc8051_rom.ngo"
Release 7.1.04i - edif2ngd H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
INFO:NgdBuild - Release 7.1.04i edif2ngd H.42
INFO:NgdBuild - Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
Writing module to "e:/vhdl/f8051/_ngo/mc8051_rom.ngo"...
Loading design module "e:\vhdl\f8051\_ngo\mc8051_rom.ngo"...
Executing edif2ngd -noa "mc8051_ram.edn" "e:\vhdl\f8051\_ngo\mc8051_ram.ngo"
Release 7.1.04i - edif2ngd H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
INFO:NgdBuild - Release 7.1.04i edif2ngd H.42
INFO:NgdBuild - Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
Writing module to "e:/vhdl/f8051/_ngo/mc8051_ram.ngo"...
Loading design module "e:\vhdl\f8051\_ngo\mc8051_ram.ngo"...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "mc8051_top.ngd" ...

Writing NGDBUILD log file "mc8051_top.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s200ft256-5".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Number of Slice Flip Flops:         590 out of   3,840   15%
  Number of 4 input LUTs:           2,850 out of   3,840   74%
Logic Distribution:
  Number of occupied Slices:                        1,655 out of   1,920   86%
    Number of Slices containing only related logic:   1,655 out of   1,655  100%
    Number of Slices containing unrelated logic:          0 out of   1,655    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          2,914 out of   3,840   75%
  Number used as logic:              2,850
  Number used as a route-thru:          48
  Number used for Dual Port RAMs:       16
    (Two LUTs used per Dual Port RAM)
  Number of bonded IOBs:               74 out of     173   42%
  Number of Block RAMs:                2 out of      12   16%
  Number of MULT18X18s:                1 out of      12    8%
  Number of GCLKs:                     2 out of       8   25%

Total equivalent gate count for design:  159,961
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  131 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "mc8051_top_map.mrp" for details.




Started process "Place & Route".




Constraints file: mc8051_top.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx.
   "mc8051_top" is an NCD, version 3.1, device xc3s200, package ft256, speed -5

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.37 2005-07-22".


Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs             0 out of 74      0%

   Number of MULT18X18s                1 out of 12      8%
   Number of RAMB16s                   2 out of 12     16%
   Number of Slices                 1655 out of 1920   86%
      Number of SLICEMs               40 out of 960     4%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98f55c) REAL time: 3 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 3 secs 

Phase 3.2



Phase 3.2 (Checksum:1c9c37d) REAL time: 3 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 4 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 4 secs 

Phase 6.8
...............................................................
Phase 6.8 (Checksum:c86f49) REAL time: 10 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 10 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 13 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 13 secs 

Writing design to file mc8051_top.ncd


Total REAL time to Placer completion: 14 secs 
Total CPU time to Placer completion: 13 secs 

Starting Router

Phase 1: 11607 unrouted;       REAL time: 15 secs 

Phase 2: 11087 unrouted;       REAL time: 15 secs 

Phase 3: 5748 unrouted;       REAL time: 17 secs 

Phase 4: 0 unrouted;       REAL time: 23 secs 


Total REAL time to Router completion: 23 secs 
Total CPU time to Router completion: 23 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           s_clk_pre |      BUFGMUX3| No   |  449 |  0.003     |  0.883      |
+---------------------+--------------+------+------+------------+-------------+
|               clk_c |      BUFGMUX7| No   |    3 |  0.000     |  0.880      |
+---------------------+--------------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 26 secs 
Total CPU time to PAR completion: 25 secs 

Peak Memory Usage:  98 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file mc8051_top.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx.
   "mc8051_top" is an NCD, version 3.1, device xc3s200, package ft256, speed -5

Analysis completed Fri Jun 01 11:43:49 2007
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 18 secs 







Started process "Generate Programming File".



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Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\vhdl\f8051/_ngo -nt timestamp -uc
myucf.ucf -p xc3s200-ft256-5 mc8051_top.edn mc8051_top.ngd 

Reading module "mc8051_top.ngo" ( "mc8051_top.ngo" unchanged since last run )...
Reading NGO file 'e:/vhdl/f8051/_ngo/mc8051_top.ngo' ...
Reading module "mc8051_rom.ngo" ( "mc8051_rom.ngo" unchanged since last run )...
Loading design module "e:\vhdl\f8051\_ngo\mc8051_rom.ngo"...
Reading module "mc8051_ram.ngo" ( "mc8051_ram.ngo" unchanged since last run )...
Loading design module "e:\vhdl\f8051\_ngo\mc8051_ram.ngo"...

Applying constraints in "myucf.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "mc8051_top.ngd" ...

Writing NGDBUILD log file "mc8051_top.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s200ft256-5".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...