layer0.tlg

8051VHDL原代码

@N:"E:\vhdl\f8051\control_mem.vhd":9:7:9:17|Synthesizing work.control_mem.rtl 
@N: CD231 :"E:\vhdl\f8051\mc8051_p.vhd":195:15:195:16|Using onehot encoding for type t_state (startup="10000")
@W:"E:\vhdl\f8051\control_mem.vhd":735:6:735:19|OTHERS clause is not synthesized 
Post processing for work.control_mem.rtl
@N: CL134 :"E:\vhdl\f8051\control_mem.vhd":936:4:936:5|Found RAM s_r0, depth=8, width=8