control_mem.plg

来自「8051VHDL原代码」· PLG 代码 · 共 13 行

@P:  Worst Slack : 981.389
@P:  control_mem|clk - Estimated Frequency : 53.7 MHz
@P:  control_mem|clk - Requested Frequency : 1.0 MHz
@P:  control_mem|clk - Estimated Period : 18.611
@P:  control_mem|clk - Requested Period : 1000.000
@P:  control_mem|clk - Slack : 981.389
@P: control_mem Part : xc3s200ft256-5
@P: control_mem I/O primitives : 374
@P: control_mem I/O Register bits : 4
@P: control_mem Register bits (Non I/O) : 473 (12%)
@P: control_mem Dual Port Rams (RAM16X1D) : 8
@P: control_mem Total Luts : 1338 (34%)