control_mem_srr.htm

8051VHDL原代码

Duplicate Module/Entity Name RAMB16_S36, appending...
Duplicate Module/Entity Name RAMB16_S36_S36, appending...
Duplicate Module/Entity Name RAMB16_S4, appending...
Duplicate Module/Entity Name RAMB16_S4_S18, appending...
Duplicate Module/Entity Name RAMB16_S4_S36, appending...
Duplicate Module/Entity Name RAMB16_S4_S4, appending...
Duplicate Module/Entity Name RAMB16_S4_S9, appending...
Duplicate Module/Entity Name RAMB16_S9, appending...
Duplicate Module/Entity Name RAMB16_S9_S18, appending...
Duplicate Module/Entity Name RAMB16_S9_S36, appending...
Duplicate Module/Entity Name RAMB16_S9_S9, appending...
Duplicate Module/Entity Name RAMB32_S64_ECC, appending...
Duplicate Module/Entity Name RAMB4_S1, appending...
Duplicate Module/Entity Name RAMB4_S16, appending...
Duplicate Module/Entity Name RAMB4_S16_S16, appending...
Duplicate Module/Entity Name RAMB4_S1_S1, appending...
Duplicate Module/Entity Name RAMB4_S1_S16, appending...
Duplicate Module/Entity Name RAMB4_S1_S2, appending...
Duplicate Module/Entity Name RAMB4_S1_S4, appending...
Duplicate Module/Entity Name RAMB4_S1_S8, appending...
Duplicate Module/Entity Name RAMB4_S2, appending...
Duplicate Module/Entity Name RAMB4_S2_S16, appending...
Duplicate Module/Entity Name RAMB4_S2_S2, appending...
Duplicate Module/Entity Name RAMB4_S2_S4, appending...
Duplicate Module/Entity Name RAMB4_S2_S8, appending...
Duplicate Module/Entity Name RAMB4_S4, appending...
Duplicate Module/Entity Name RAMB4_S4_S16, appending...
Duplicate Module/Entity Name RAMB4_S4_S4, appending...
Duplicate Module/Entity Name RAMB4_S4_S8, appending...
Duplicate Module/Entity Name RAMB4_S8, appending...
Duplicate Module/Entity Name RAMB4_S8_S16, appending...
Duplicate Module/Entity Name RAMB4_S8_S8, appending...
Duplicate Module/Entity Name ROM128X1, appending...
Duplicate Module/Entity Name ROM16X1, appending...
Duplicate Module/Entity Name ROM256X1, appending...
Duplicate Module/Entity Name ROM32X1, appending...
Duplicate Module/Entity Name ROM64X1, appending...
Duplicate Module/Entity Name SRL16, appending...
Duplicate Module/Entity Name SRL16_1, appending...
Duplicate Module/Entity Name SRL16E, appending...
Duplicate Module/Entity Name SRL16E_1, appending...
Duplicate Module/Entity Name SRLC16, appending...
Duplicate Module/Entity Name SRLC16_1, appending...
Duplicate Module/Entity Name SRLC16E, appending...
Duplicate Module/Entity Name SRLC16E_1, appending...
Duplicate Module/Entity Name STARTUP_FPGACORE, appending...
Duplicate Module/Entity Name STARTUP_SPARTAN2, appending...
Duplicate Module/Entity Name STARTUP_SPARTAN3, appending...
Duplicate Module/Entity Name STARTUP_SPARTAN3E, appending...
Duplicate Module/Entity Name STARTUP_VIRTEX, appending...
Duplicate Module/Entity Name STARTUP_VIRTEX2, appending...
Duplicate Module/Entity Name STARTUP_VIRTEX4, appending...
Duplicate Module/Entity Name TBLOCK, appending...
Duplicate Module/Entity Name TIMEGRP, appending...
Duplicate Module/Entity Name TIMESPEC, appending...
Duplicate Module/Entity Name USR_ACCESS_VIRTEX4, appending...
Duplicate Module/Entity Name VCC, appending...
Duplicate Module/Entity Name XNOR2, appending...
Duplicate Module/Entity Name XNOR3, appending...
Duplicate Module/Entity Name XNOR4, appending...
Duplicate Module/Entity Name XNOR5, appending...
Duplicate Module/Entity Name XOR2, appending...
Duplicate Module/Entity Name XOR3, appending...
Duplicate Module/Entity Name XOR4, appending...
Duplicate Module/Entity Name XOR5, appending...
Duplicate Module/Entity Name XORCY, appending...
Duplicate Module/Entity Name XORCY_D, appending...
Duplicate Module/Entity Name XORCY_L, appending...
Duplicate Module/Entity Name STARTUP_VIRTEX2_CLK, appending...
Duplicate Module/Entity Name STARTUP_VIRTEX2_GSR, appending...
Duplicate Module/Entity Name STARTUP_VIRTEX2_GTS, appending...
Duplicate Module/Entity Name STARTUP_VIRTEX2_GHIGH, appending...
Duplicate Module/Entity Name STARTUP_VIRTEX2_GWE, appending...
Duplicate Module/Entity Name STARTUP_VIRTEX2_ALL, appending...
Duplicate Module/Entity Name STARTUP_VIRTEX_CLK, appending...
Duplicate Module/Entity Name STARTUP_VIRTEX_GSR, appending...
Duplicate Module/Entity Name STARTUP_VIRTEX_GTS, appending...
Duplicate Module/Entity Name STARTUP_VIRTEX_ALL, appending...
Duplicate Module/Entity Name STARTUP_SPARTAN2_CLK, appending...
Duplicate Module/Entity Name STARTUP_SPARTAN2_GSR, appending...
Duplicate Module/Entity Name STARTUP_SPARTAN2_GTS, appending...
Duplicate Module/Entity Name STARTUP_SPARTAN2_ALL, appending...
VHDL syntax check successful!
@N: : <a href="e:\vhdl\f8051\control_mem.vhd:9:7:9:18:@N::@XP_MSG">control_mem.vhd(9)</a><!@TM:1180666672> | Synthesizing work.control_mem.rtl 
@N:<a href="@N:CD231:@XP_HELP">CD231</a> : <a href="e:\vhdl\f8051\mc8051_p.vhd:195:15:195:17:@N:CD231:@XP_MSG">mc8051_p.vhd(195)</a><!@TM:1180666672> | Using onehot encoding for type t_state (startup="10000")
<font color=#A52A2A>@W: : <a href="e:\vhdl\f8051\control_mem.vhd:735:6:735:20:@W::@XP_MSG">control_mem.vhd(735)</a><!@TM:1180666672> | OTHERS clause is not synthesized </font>
Post processing for work.control_mem.rtl
@N:<a href="@N:CL134:@XP_HELP">CL134</a> : <a href="e:\vhdl\f8051\control_mem.vhd:936:4:936:6:@N:CL134:@XP_MSG">control_mem.vhd(936)</a><!@TM:1180666672> | Found RAM s_r0, depth=8, width=8
# Fri Jun 01 10:56:47 2007

Synplicity Netlist Filter, version 3.1.0, Build 044R, built Apr 27 2005
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jun 01 10:56:48 2007

@END
Process took 0h:00m:57s realtime, 0h:00m:57s cputime
# Fri Jun 01 10:56:48 2007

###########################################################[
Version 8.1
<a name=mapperReport2>Synplicity Xilinx Technology Mapper, Version 8.1.0, Build 540R, Built May  9 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved
Reading constraint file: e:\vhdl\f8051\control_mem.sdc
Reading Xilinx I/O pad type table from file &ltd:\Program Files\Synplicity\fpga_81\lib/xilinx/x_io_tbl.txt> 
Reading Xilinx Rocket I/O parameter type table from file &ltd:\Program Files\Synplicity\fpga_81\lib/xilinx/gttype.txt> 


RTL optimization done.
@N:<a href="@N:MF135:@XP_HELP">MF135</a> : <a href="e:\vhdl\f8051\control_mem.vhd:936:4:936:6:@N:MF135:@XP_MSG">control_mem.vhd(936)</a><!@TM:1180666672> | Found RAM, 's_r0[7:0]', 8 words by 8 bits 
@N: : <a href="e:\vhdl\f8051\control_mem.vhd:936:4:936:6:@N::@XP_MSG">control_mem.vhd(936)</a><!@TM:1180666672> | Found updn counter in view:work.control_mem(rtl) inst sp[7:0] 

Clock Buffers:
  Inserting Clock buffer for port clk,	TNM=clk

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
------------------------------------------------------------

Net buffering Report for view:work.control_mem(rtl):
@N:<a href="@N:FX103:@XP_HELP">FX103</a> : <a href="e:\vhdl\f8051\control_mem.vhd:702:4:702:8:@N:FX103:@XP_MSG">control_mem.vhd(702)</a><!@TM:1180666672> | Instance "s_bdata_u_0" with "115" loads has been replicated "1" time(s) due to a soft fanout limit of "100" 
@N:<a href="@N:FX104:@XP_HELP">FX104</a> : <!@TM:1180666672> | Net "regs_wr_en_i_c[1]" with "136" loads has been buffered by "2" buffers due to a soft fanout limit of "100"  
Added 2 Buffers
Added 0 Registers via replication
Added 1 LUTs via replication

@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1180666672> | The option to pack flops in the IOB has not been specified  
Writing Analyst data base e:\vhdl\f8051\control_mem.srm
Writing EDIF Netlist and constraint files
Found clock control_mem|clk with period 1000.00ns 


<a name=timingReport3>##### START OF TIMING REPORT #####[
# Timing Report written on Fri Jun 01 10:57:49 2007
#


Top view:               control_mem
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        0
Constraint File(s):    e:\vhdl\f8051\control_mem.sdc
                       
@N:<a href="@N:MT195:@XP_HELP">MT195</a> : <!@TM:1180666672> | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. 

@N:<a href="@N:MT197:@XP_HELP">MT197</a> : <!@TM:1180666672> | Clock constraints cover only FF-to-FF paths associated with the clock.. 



<a name=performanceSummary4>Performance Summary 
*******************


Worst slack in design: 981.389

                    Requested     Estimated     Requested     Estimated                 Clock        Clock              
Starting Clock      Frequency     Frequency     Period        Period        Slack       Type         Group              
------------------------------------------------------------------------------------------------------------------------
control_mem|clk     1.0 MHz       53.7 MHz      1000.000      18.611        981.389     inferred     Inferred_clkgroup_0
========================================================================================================================





<a name=clockRelationships5>Clock Relationships
*******************

Clocks                            |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
--------------------------------------------------------------------------------------------------------------------------
Starting         Ending           |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
--------------------------------------------------------------------------------------------------------------------------
control_mem|clk  control_mem|clk  |  1000.000    981.389  |  No paths    -      |  No paths    -      |  No paths    -    
==========================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



<a name=interfaceInfo6>Interface Information 
*********************

		No IO constraint found 


##### END OF TIMING REPORT #####]

---------------------------------------
<a name=resourceUsage7>Resource Usage Report for control_mem 

Mapping to part: xc3s200ft256-5
Cell usage:
BUF             2 uses
FDC             84 uses
FDCE            319 uses
FDP             42 uses
FDPE            32 uses
GND             1 use
MULT_AND        8 uses
MUXCY_L         50 uses
MUXF5           181 uses
MUXF6           50 uses
MUXF7           14 uses
MUXF8           2 uses
VCC             1 use
XORCY           53 uses
LUT1            14 uses
LUT2            131 uses
LUT3            700 uses
LUT4            477 uses

I/O primitives: 374
IBUF           171 uses
OBUF           203 uses

BUFGP          1 use

I/O Register bits:                  4
Register bits not including I/Os:   473 (12%)

RAM/ROM usage summary
Dual Port Rams (RAM16X1D): 8


Global Clock Buffers: 1 of 8 (12%)


Mapping Summary:
Total  LUTs: 1338 (34%)

Mapper successful!
Process took 0h:1m:0s realtime, 0h:1m:0s cputime
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