mc8051_top.par

8051VHDL原代码

Release 7.1i par H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D-99CFECE026174::  Thu Oct 25 20:45:53 2007

par -w -intstyle ise -ol std -t 1 mc8051_top_map.ncd mc8051_top.ncd
mc8051_top.pcf 


Constraints file: mc8051_top.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
D:/Xilinx.
   "mc8051_top" is an NCD, version 3.1, device xc3s200, package ft256, speed -5

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "ADVANCED 1.35 2005-01-22".


Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs            10 out of 74     13%

   Number of MULT18X18s                1 out of 12      8%
   Number of RAMB16s                   2 out of 12     16%
   Number of Slices                 1583 out of 1920   82%
      Number of SLICEMs               50 out of 960     5%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98f106) REAL time: 4 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 4 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 4 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 4 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 4 secs 

Phase 6.8
.........................................
Phase 6.8 (Checksum:d378e9) REAL time: 12 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 12 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 16 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 16 secs 

Writing design to file mc8051_top.ncd


Total REAL time to Placer completion: 17 secs 
Total CPU time to Placer completion: 14 secs 

Starting Router

Phase 1: 11146 unrouted;       REAL time: 17 secs 

Phase 2: 10685 unrouted;       REAL time: 18 secs 

Phase 3: 5832 unrouted;       REAL time: 20 secs 

Phase 4: 0 unrouted;       REAL time: 32 secs 


Total REAL time to Router completion: 32 secs 
Total CPU time to Router completion: 26 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           s_clk_pre |      BUFGMUX5| No   |  396 |  0.004     |  0.884      |
+---------------------+--------------+------+------+------------+-------------+
|               clk_c |      BUFGMUX0| No   |    3 |  0.000     |  0.880      |
+---------------------+--------------+------+------+------------+-------------+

INFO:Par:340 - 
   The Delay report will not be generated when running non-timing driven PAR
   with effort level Standard or Medium. If a delay report is required please do
   one of the following:  1) use effort level High, 2) use the following
   environment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timing
   constraints for the design.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 36 secs 
Total CPU time to PAR completion: 28 secs 

Peak Memory Usage:  97 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file mc8051_top.ncd



PAR done!