📄 mc8051_siu.vhd
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when ("0010") => -- D1
if s_m13_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("0011") => -- D2
if s_m13_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("0100") => -- D3
if s_m13_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("0101") => -- D4
if s_m13_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("0110") => -- D5
if s_m13_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("0111") => -- D6
if s_m13_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("1000") => -- D7
if s_m13_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("1001") => -- D8
if s_m13_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("1010") => -- D9 = STOP BIT
-- store data and set interrupt bit if conditions are met.
if (s_ri = '0' and s_sm2 = '0') or
(s_ri = '0' and s_rxd_val = '1') then
if s_m13_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "10";
s_recv_done <= '1';
s_rb8 <= s_rxd_val;
s_recv_buf <= s_recv_sh(7 downto 0);
end if;
-- forget data and recommence listening for a start bit
else
if s_m13_rxshift_en = '1' then
v_rxstep := "10";
end if;
end if;
when others =>
v_rxstep := "10";
end case;
-------------------------------------------------------------------------------
-- MODE 2
-------------------------------------------------------------------------------
when ("10") =>
case s_recv_state is
when ("0000") => -- synchronise reception
if s_ren = '1' and s_detect = '1' then
v_rxstep := "01";
s_recv_sh <= conv_unsigned(0,8);
s_recv_done <= '0';
end if;
when ("0001") => -- D0 = START BIT
if s_rxd_val = '0' then
if s_m2_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
else -- reject false start bits
if s_m2_rxshift_en = '1' then
v_rxstep := "10";
end if;
end if;
when ("0010") => -- D1
if s_m2_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("0011") => -- D2
if s_m2_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("0100") => -- D3
if s_m2_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("0101") => -- D4
if s_m2_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("0110") => -- D5
if s_m2_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("0111") => -- D6
if s_m2_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("1000") => -- D7
if s_m2_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("1001") => -- D8
if s_m2_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("1010") => -- D9
-- store data and set interrupt bit if conditions are met.
if (s_ri = '0' and s_sm2 = '0') or
(s_ri = '0' and s_rxd_val = '1') then
if s_m2_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
s_recv_done <= '1';
s_rb8 <= s_rxd_val;
s_recv_buf <= s_recv_sh(7 downto 0);
end if;
end if;
-- forget data
if s_m2_rxshift_en = '1' then
v_rxstep := "01";
end if;
when ("1011") => -- D10 STOP BIT
-- recommence listening for a start bit
if s_m2_rxshift_en = '1' then
-- s_recv_state <= conv_unsigned(0,4);
v_rxstep := "10";
end if;
when others =>
-- s_recv_state <= conv_unsigned(0,4);
v_rxstep := "10";
end case;
-------------------------------------------------------------------------------
-- MODE 3
-------------------------------------------------------------------------------
when ("11") =>
case s_recv_state is
when ("0000") => -- synchronise reception
if s_ren = '1' and s_detect = '1' then
v_rxstep := "01";
s_recv_sh <= conv_unsigned(0,8);
s_recv_done <= '0';
end if;
when ("0001") => -- D0 = START BIT
if s_detect = '0' then
if s_rxd_val = '0' then
if s_m13_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
else -- reject false start bits
if s_m13_rxshift_en = '1' then
v_rxstep := "10";
end if;
end if;
end if;
when ("0010") => -- D1
if s_m13_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("0011") => -- D2
if s_m13_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("0100") => -- D3
if s_m13_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("0101") => -- D4
if s_m13_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("0110") => -- D5
if s_m13_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("0111") => -- D6
if s_m13_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("1000") => -- D7
if s_m13_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("1001") => -- D8
if s_m13_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
v_rxstep := "01";
end if;
when ("1010") => -- D9
-- store data and set interrupt bit if conditions are met.
if (s_ri = '0' and s_sm2 = '0') or
(s_ri = '0' and s_rxd_val = '1') then
if s_m13_rxshift_en = '1' then
s_recv_sh(7) <= s_rxd_val;
s_recv_sh(6 downto 0) <= s_recv_sh(7 downto 1);
s_recv_done <= '1';
s_rb8 <= s_rxd_val;
s_recv_buf <= s_recv_sh(7 downto 0);
end if;
end if;
-- forget data
if s_m13_rxshift_en = '1' then
v_rxstep := "01";
end if;
when ("1011") => -- D10 STOP BIT
-- recommence listening for a start bit
if s_m13_rxshift_en = '1' then
v_rxstep := "10";
end if;
when others =>
v_rxstep := "10";
end case;
when others =>
null;
end case;
case v_rxstep is
when "01" =>
s_recv_state <= s_recv_state + conv_unsigned(1,1);
when "10" =>
s_recv_state <= conv_unsigned(0,4);
when others =>
null;
end case;
end if;
end if;
end process p_receive;
end rtl;
-------------------------------------------------------------------------------
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