liid.fit.rpt

利用fpga实现vga解码

; Use smart compilation                                              ; Off                            ; Off                            ;
; Maximum processors allowed for parallel compilation                ; 1                              ; 1                              ;
; Use TimeQuest Timing Analyzer                                      ; Off                            ; Off                            ;
; Router Timing Optimization Level                                   ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                        ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                        ; Off                            ; Off                            ;
; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                        ; Off                            ; Off                            ;
; PowerPlay Power Optimization                                       ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                         ; On                             ; On                             ;
; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
; PCI I/O                                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                 ; Off                            ; Off                            ;
; Auto Packed Registers                                              ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                  ; On                             ; On                             ;
; Auto Merge PLLs                                                    ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                  ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                        ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
; Auto Global Clock                                                  ; On                             ; On                             ;
; Auto Global Register Control Signals                               ; On                             ; On                             ;
; Stop After Congestion Map Generation                               ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                  ; Off                            ; Off                            ;
; Maximum number of global clocks allowed                            ; -1                             ; -1                             ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Partition Preservation Settings                                                                                                                ;
+--------------------------------+-------------------+---------+------------------------------+------------------------+--------------------------------+
; Name                           ; # Preserved Nodes ; # Nodes ; Preservation Level Requested ; Netlist Type Used      ; Hierarchy                      ;
+--------------------------------+-------------------+---------+------------------------------+------------------------+--------------------------------+
; Top                            ; 0                 ; 331     ; Placement and Routing        ; Post-Synthesis Netlist ;                                ;
; sld_signaltap:auto_signaltap_0 ; 0                 ; 849     ; Placement and Routing        ; Post-Synthesis Netlist ; sld_signaltap:auto_signaltap_0 ;
; sld_hub:sld_hub_inst           ; 0                 ; 176     ; Placement and Routing        ; Post-Synthesis Netlist ; sld_hub:sld_hub_inst           ;
+--------------------------------+-------------------+---------+------------------------------+------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/baby/lab_dream/Liid/liid.pin.


+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                                                                        ;
+---------------------------------------------+----------------------------------------------------------------------------------------+
; Resource                                    ; Usage                                                                                  ;
+---------------------------------------------+----------------------------------------------------------------------------------------+
; Total logic elements                        ; 893 / 8,256 ( 11 % )                                                                   ;
;     -- Combinational with no register       ; 201                                                                                    ;
;     -- Register only                        ; 328                                                                                    ;
;     -- Combinational with a register        ; 364                                                                                    ;
;                                             ;                                                                                        ;
; Logic element usage by number of LUT inputs ;                                                                                        ;
;     -- 4 input functions                    ; 212                                                                                    ;
;     -- 3 input functions                    ; 123                                                                                    ;
;     -- <=2 input functions                  ; 230                                                                                    ;
;     -- Register only                        ; 328                                                                                    ;
;                                             ;                                                                                        ;
; Logic elements by mode                      ;                                                                                        ;
;     -- normal mode                          ; 477                                                                                    ;
;     -- arithmetic mode                      ; 88                                                                                     ;
;                                             ;                                                                                        ;
; Total registers*                            ; 692 / 8,646 ( 8 % )                                                                    ;
;     -- Dedicated logic registers            ; 692 / 8,256 ( 8 % )                                                                    ;
;     -- I/O registers                        ; 0 / 390 ( 0 % )                                                                        ;
;                                             ;                                                                                        ;
; Total LABs:  partially or completely used   ; 90 / 516 ( 17 % )                                                                      ;
; User inserted logic elements                ; 0                                                                                      ;
; Virtual pins                                ; 21                                                                                     ;
; I/O pins                                    ; 46 / 138 ( 33 % )                                                                      ;
;     -- Clock pins                           ; 1 / 4 ( 25 % )                                                                         ;
; Global signals                              ; 5                                                                                      ;
; M4Ks                                        ; 2 / 36 ( 6 % )                                                                         ;
; Total memory bits                           ; 4,228 / 165,888 ( 3 % )                                                                ;
; Total RAM block bits                        ; 9,216 / 165,888 ( 6 % )                                                                ;
; Embedded Multiplier 9-bit elements          ; 0 / 36 ( 0 % )                                                                         ;
; PLLs                                        ; 0 / 2 ( 0 % )                                                                          ;