liid.map.qmsg

利用fpga实现vga解码

{ "Info" "ISGN_AE_SUCCESSFUL" "auto_signaltap_0 " "Info: Analysis and Synthesis generated SignalTap II or debug node instance \"auto_signaltap_0\"" {  } {  } 0 0 "Analysis and Synthesis generated SignalTap II or debug node instance \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "addr_from_arm\[7\] data_in GND " "Warning (14130): Reduced register \"addr_from_arm\[7\]\" with stuck data_in port to stuck value GND" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 44 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "addr_from_arm\[6\] data_in GND " "Warning (14130): Reduced register \"addr_from_arm\[6\]\" with stuck data_in port to stuck value GND" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 44 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WOPT_RAM_PASS_THROUGH_LOGIC_INSERTED_ALTSYNCRAM" "video_buffer:video_bufferk\|ram__dual~0 " "Warning: Inferred RAM node \"video_buffer:video_bufferk\|ram__dual~0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } { { "src/video_buffer.v" "ram__dual~0" { Text "D:/baby/lab_dream/Liid/src/video_buffer.v" 21 -1 0 } }  } 0 0 "Inferred RAM node \"%1!s!\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "video_buffer:video_bufferk\|ram__dual_0_bypass\[13\] data_in GND " "Warning (14130): Reduced register \"video_buffer:video_bufferk\|ram__dual_0_bypass\[13\]\" with stuck data_in port to stuck value GND" {  } {  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "video_buffer:video_bufferk\|ram__dual_0_bypass\[15\] data_in GND " "Warning (14130): Reduced register \"video_buffer:video_bufferk\|ram__dual_0_bypass\[15\]\" with stuck data_in port to stuck value GND" {  } {  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "video_buffer:video_bufferk\|ram__dual_0_bypass\[16\] addr_b_inc\[7\] " "Info (13350): Duplicate register \"video_buffer:video_bufferk\|ram__dual_0_bypass\[16\]\" merged to single register \"addr_b_inc\[7\]\"" {  } {  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "video_buffer:video_bufferk\|ram__dual_0_bypass\[14\] addr_b_inc\[6\] " "Info (13350): Duplicate register \"video_buffer:video_bufferk\|ram__dual_0_bypass\[14\]\" merged to single register \"addr_b_inc\[6\]\"" {  } {  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "video_buffer:video_bufferk\|ram__dual_0_bypass\[12\] addr_b_inc\[5\] " "Info (13350): Duplicate register \"video_buffer:video_bufferk\|ram__dual_0_bypass\[12\]\" merged to single register \"addr_b_inc\[5\]\"" {  } {  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "video_buffer:video_bufferk\|ram__dual_0_bypass\[10\] addr_b_inc\[4\] " "Info (13350): Duplicate register \"video_buffer:video_bufferk\|ram__dual_0_bypass\[10\]\" merged to single register \"addr_b_inc\[4\]\"" {  } {  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "video_buffer:video_bufferk\|ram__dual_0_bypass\[8\] addr_b_inc\[3\] " "Info (13350): Duplicate register \"video_buffer:video_bufferk\|ram__dual_0_bypass\[8\]\" merged to single register \"addr_b_inc\[3\]\"" {  } {  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "video_buffer:video_bufferk\|ram__dual_0_bypass\[6\] addr_b_inc\[2\] " "Info (13350): Duplicate register \"video_buffer:video_bufferk\|ram__dual_0_bypass\[6\]\" merged to single register \"addr_b_inc\[2\]\"" {  } {  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "video_buffer:video_bufferk\|ram__dual_0_bypass\[4\] addr_b_inc\[1\] " "Info (13350): Duplicate register \"video_buffer:video_bufferk\|ram__dual_0_bypass\[4\]\" merged to single register \"addr_b_inc\[1\]\"" {  } {  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "video_buffer:video_bufferk\|ram__dual_0_bypass\[2\] addr_b_inc\[0\] " "Info (13350): Duplicate register \"video_buffer:video_bufferk\|ram__dual_0_bypass\[2\]\" merged to single register \"addr_b_inc\[0\]\"" {  } {  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_ALTSYNCRAM_INFERRED" "video_buffer:video_bufferk\|ram__dual~0 " "Info: Inferred altsyncram megafunction from the following design logic: \"video_buffer:video_bufferk\|ram__dual~0\" " { { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Info: Parameter OPERATION_MODE set to DUAL_PORT" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 4 " "Info: Parameter WIDTH_A set to 4" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 8 " "Info: Parameter WIDTHAD_A set to 8" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 129 " "Info: Parameter NUMWORDS_A set to 129" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 4 " "Info: Parameter WIDTH_B set to 4" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 8 " "Info: Parameter WIDTHAD_B set to 8" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 129 " "Info: Parameter NUMWORDS_B set to 129" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Info: Parameter ADDRESS_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Info: Parameter OUTDATA_REG_B set to UNREGISTERED" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Info: Parameter ADDRESS_ACLR_B set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Info: Parameter OUTDATA_ACLR_B set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Info: Parameter ADDRESS_REG_B set to CLOCK0" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Info: Parameter INDATA_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Info: Parameter WRCONTROL_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "RAM_BLOCK_TYPE AUTO " "Info: Parameter RAM_BLOCK_TYPE set to AUTO" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Info: Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 0}  } { { "src/video_buffer.v" "ram__dual~0" { Text "D:/baby/lab_dream/Liid/src/video_buffer.v" 21 -1 0 } }  } 0 0 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|segment_shift_clk_ena sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|buffer_write_enable_delayed " "Info (13350): Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|segment_shift_clk_ena\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|buffer_write_enable_delayed\"" {  } { { "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" 824 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[0\] sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[0\] " "Info (13350): Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[0\]\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[0\]\"" {  } { { "c:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[1\] sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[1\] " "Info (13350): Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[1\]\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[1\]\"" {  } { { "c:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[2\] sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[2\] " "Info (13350): Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[2\]\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[2\]\"" {  } { { "c:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[3\] sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[3\] " "Info (13350): Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[3\]\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[3\]\"" {  } { { "c:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[4\] sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[4\] " "Info (13350): Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[4\]\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[4\]\"" {  } { { "c:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[5\] sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[5\] " "Info (13350): Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[5\]\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[5\]\"" {  } { { "c:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[6\] sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[6\] " "Info (13350): Duplicate register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count\[6\]\" merged to single register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|next_address\[6\]\"" {  } { { "c:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "video_buffer:video_bufferk\|altsyncram:ram__dual_rtl_0 " "Info: Elaborated megafunction instantiation \"video_buffer:video_bufferk\|altsyncram:ram__dual_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "video_buffer:video_bufferk\|altsyncram:ram__dual_rtl_0 " "Info: Instantiated megafunction \"video_buffer:video_bufferk\|altsyncram:ram__dual_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Info: Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 4 " "Info: Parameter \"WIDTH_A\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 8 " "Info: Parameter \"WIDTHAD_A\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 129 " "Info: Parameter \"NUMWORDS_A\" = \"129\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 4 " "Info: Parameter \"WIDTH_B\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 8 " "Info: Parameter \"WIDTHAD_B\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 129 " "Info: Parameter \"NUMWORDS_B\" = \"129\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Info: Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B UNREGISTERED " "Info: Parameter \"OUTDATA_REG_B\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Info: Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Info: Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK0 " "Info: Parameter \"ADDRESS_REG_B\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Info: Parameter \"INDATA_ACLR_A\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Info: Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "RAM_BLOCK_TYPE AUTO " "Info: Parameter \"RAM_BLOCK_TYPE\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Info: Parameter \"READ_DURING_WRITE_MODE_MIXED_PORTS\" = \"OLD_DATA\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_jpi1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_jpi1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_jpi1 " "Info: Found entity 1: altsyncram_jpi1" {  } { { "db/altsyncram_jpi1.tdf" "" { Text "D:/baby/lab_dream/Liid/db/altsyncram_jpi1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "high VCC " "Warning (13410): Pin \"high\" is stuck at VCC" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 22 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 0}
{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Info: Found the following redundant logic cells in design" {  } {  } 0 0 "Found the following redundant logic cells in design" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "c:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 0}
{ "Critical Warning" "WAMERGE_TAP_SOURCE_DOES_NOT_EXIST" "sld_signaltap:auto_signaltap_0 addr_b_from_key\[0\] " "Critical Warning: Can't connect signal \"addr_b_from_key\[0\]\" to SignalTap II instance \"sld_signaltap:auto_signaltap_0\" because the signal does not exist" {  } {  } 1 0 "Can't connect signal \"%2!s!\" to SignalTap II instance \"%1!s!\" because the signal does not exist" 0 0 "" 0 0}
{ "Critical Warning" "WAMERGE_TAP_SOURCE_DOES_NOT_EXIST" "sld_signaltap:auto_signaltap_0 addr_b_from_key\[0\] " "Critical Warning: Can't connect signal \"addr_b_from_key\[0\]\" to SignalTap II instance \"sld_signaltap:auto_signaltap_0\" because the signal does not exist" {  } {  } 1 0 "Can't connect signal \"%2!s!\" to SignalTap II instance \"%1!s!\" because the signal does not exist" 0 0 "" 0 0}
{ "Critical Warning" "WAMERGE_TAP_SOURCE_DOES_NOT_EXIST" "sld_signaltap:auto_signaltap_0 addr_b_from_key\[1\] " "Critical Warning: Can't connect signal \"addr_b_from_key\[1\]\" to SignalTap II instance \"sld_signaltap:auto_signaltap_0\" because the signal does not exist" {  } {  } 1 0 "Can't connect signal \"%2!s!\" to SignalTap II instance \"%1!s!\" because the signal does not exist" 0 0 "" 0 0}