liid.hif

利用fpga实现vga解码

-1
3
q1
-1
3
q0
-1
3
enable
-1
3
clock
-1
3
aclr
-1
3
}
# include_file {
c:|altera|80|quartus|libraries|megafunctions|lpm_constant.inc
dcde44eee59335c1e2fe75d574f9646
c:|altera|80|quartus|libraries|megafunctions|aglobal80.inc
9274497d636e3ed37111b8c54bf938
c:|altera|80|quartus|libraries|megafunctions|dffeea.inc
55d29d20f7e852c37746bec4e2495ec
}
# macro_sequence

# end
# entity
lpm_decode
# storage
db|liid.(93).cnf
db|liid.(93).cnf
# case_insensitive
# source_file
c:|altera|80|quartus|libraries|megafunctions|lpm_decode.tdf
50b819a7794191b866806437cffb1b95
6
# user_parameter {
LPM_WIDTH
3
PARAMETER_SIGNED_DEC
USR
LPM_DECODES
8
PARAMETER_SIGNED_DEC
USR
LPM_PIPELINE
1
PARAMETER_SIGNED_DEC
USR
CASCADE_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
decode_aoi
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
eq7
-1
3
eq3
-1
3
eq2
-1
3
eq1
-1
3
eq0
-1
3
enable
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
clken
-1
3
aclr
-1
3
}
# include_file {
c:|altera|80|quartus|libraries|megafunctions|altshift.inc
70fa13aee7d6d160ef20b2de32813a
c:|altera|80|quartus|libraries|megafunctions|lpm_compare.inc
aec4ea1b78f4cda1c3effe18f1abbf63
c:|altera|80|quartus|libraries|megafunctions|declut.inc
b1d5939399e5c04dfe1d209af8cc490
c:|altera|80|quartus|libraries|megafunctions|lpm_constant.inc
dcde44eee59335c1e2fe75d574f9646
c:|altera|80|quartus|libraries|megafunctions|aglobal80.inc
9274497d636e3ed37111b8c54bf938
}
# macro_sequence

# end
# entity
decode_aoi
# storage
db|liid.(94).cnf
db|liid.(94).cnf
# case_insensitive
# source_file
db|decode_aoi.tdf
326ac63c2d0888de57d57df5b75b0b9
6
# used_port {
eq7
-1
3
eq6
-1
3
eq5
-1
3
eq4
-1
3
eq3
-1
3
eq2
-1
3
eq1
-1
3
eq0
-1
3
enable
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
clken
-1
3
aclr
-1
3
}
# macro_sequence

# end
# entity
sld_dffex
# storage
db|liid.(95).cnf
db|liid.(95).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|80|quartus|libraries|megafunctions|sld_dffex.vhd
999fa69c107f88d40f51e5f3f197680
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
size
1
PARAMETER_SIGNED_DEC
USR
 constraint(d)
0 downto 0
PARAMETER_STRING
USR
 constraint(q)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|80|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
sld_dffex
# storage
db|liid.(96).cnf
db|liid.(96).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|80|quartus|libraries|megafunctions|sld_dffex.vhd
999fa69c107f88d40f51e5f3f197680
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
size
9
PARAMETER_SIGNED_DEC
USR
 constraint(d)
8 downto 0
PARAMETER_STRING
USR
 constraint(q)
8 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|80|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
sld_dffex
# storage
db|liid.(97).cnf
db|liid.(97).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|80|quartus|libraries|megafunctions|sld_dffex.vhd
999fa69c107f88d40f51e5f3f197680
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
size
8
PARAMETER_SIGNED_DEC
USR
 constraint(d)
7 downto 0
PARAMETER_STRING
USR
 constraint(q)
7 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|80|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
sld_rom_sr
# storage
db|liid.(98).cnf
db|liid.(98).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|80|quartus|libraries|megafunctions|sld_rom_sr.vhd
27b22ac9a7a125064e81a222ddd4a5
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
OFF
}
# user_parameter {
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
n_bits
64
PARAMETER_SIGNED_DEC
USR
word_size
4
PARAMETER_SIGNED_DEC
USR
 constraint(rom_data)
63 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|80|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
video_buffer
# storage
db|liid.(99).cnf
db|liid.(99).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
src|video_buffer.v
bf27bdba68512e767daf02147b76c7
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
DATA_WIDTH
8
PARAMETER_SIGNED_DEC
DEF
ADDR_WIDTH
10
PARAMETER_SIGNED_DEC
DEF
}
# hierarchies {
video_buffer:video_bufferk
}
# macro_sequence

# end
# entity
vga
# storage
db|liid.(100).cnf
db|liid.(100).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
src|vga_ctr.v
f08f40a16cb27651b47565faf2db74
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
vga:vgak
}
# macro_sequence

# end
# entity
sld_signaltap
# storage
db|liid.(101).cnf
db|liid.(101).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|80|quartus|libraries|megafunctions|sld_signaltap.vhd
ddf51be5d4c09eb8d9e7c1a51c8b61
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
805334528
PARAMETER_UNKNOWN
USR
SLD_IP_VERSION
6
PARAMETER_SIGNED_DEC
DEF
SLD_IP_MINOR_VERSION
0
PARAMETER_SIGNED_DEC
DEF
SLD_COMMON_IP_VERSION
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
1
PARAMETER_UNKNOWN
USR
sld_trigger_bits
1
PARAMETER_UNKNOWN
USR
SLD_NODE_CRC_BITS
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
13610
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
50274
PARAMETER_UNKNOWN
USR
SLD_INCREMENTAL_ROUTING
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
128
PARAMETER_UNKNOWN
USR
sld_segment_size
128
PARAMETER_UNKNOWN
USR
SLD_RAM_BLOCK_TYPE
AUTO
PARAMETER_STRING
DEF
sld_state_bits
11
PARAMETER_UNKNOWN
USR
sld_buffer_full_stop
1
PARAMETER_UNKNOWN
USR
SLD_MEM_ADDRESS_BITS
7
PARAMETER_SIGNED_DEC
DEF
SLD_DATA_BIT_CNTR_BITS
4
PARAMETER_SIGNED_DEC
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
SLD_ADVANCED_TRIGGER_1
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_2
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_3
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_4
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_5
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_6
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_7
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_8
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_9
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
24
PARAMETER_UNKNOWN
USR
sld_inversion_mask
000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
SLD_STATE_FLOW_MGR_ENTITY
state_flow_mgr_entity.vhd
PARAMETER_STRING
DEF
sld_state_flow_use_generated
0
PARAMETER_UNKNOWN
USR
sld_current_resource_width
1
PARAMETER_UNKNOWN
USR
sld_attribute_mem_mode
OFF
PARAMETER_UNKNOWN
USR
}
# lmf
c:|altera|80|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
sld_signaltap_impl
# storage
db|liid.(102).cnf
db|liid.(102).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|80|quartus|libraries|megafunctions|sld_signaltap.vhd
ddf51be5d4c09eb8d9e7c1a51c8b61
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sld_ip_version
6
PARAMETER_SIGNED_DEC
USR
sld_ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
sld_common_ip_version
0
PARAMETER_SIGNED_DEC
USR
sld_data_bits
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_bits
1
PARAMETER_SIGNED_DEC
USR
sld_node_crc_bits
32
PARAMETER_SIGNED_DEC
USR
sld_node_crc_hiword
13610
PARAMETER_SIGNED_DEC
USR
sld_node_crc_loword
50274
PARAMETER_SIGNED_DEC
USR
sld_incremental_routing
0
PARAMETER_SIGNED_DEC
USR
sld_sample_depth
128
PARAMETER_SIGNED_DEC
USR
sld_segment_size
128
PARAMETER_SIGNED_DEC
USR
sld_ram_block_type
AUTO
PARAMETER_STRING
USR
sld_state_bits
11
PARAMETER_SIGNED_DEC
USR
sld_buffer_full_stop
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_level
1
PARAMETER_SIGNED_DEC
USR
sld_trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
sld_trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
sld_enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_advanced_trigger_1
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_2
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_3
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_4
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_5
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_6
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_7
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_8
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_9
NONE
PARAMETER_STRING
USR
sld_advanced_trigger_10
NONE
PARAMETER_STRING
USR
sld_inversion_mask_length
24
PARAMETER_SIGNED_DEC
USR
sld_inversion_mask
000000000000000000000000
PARAMETER_UNSIGNED_BIN
USR
sld_power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
sld_state_flow_mgr_entity
state_flow_mgr_entity.vhd
PARAMETER_STRING
USR
sld_state_flow_use_generated
0
PARAMETER_SIGNED_DEC
USR
sld_current_resource_width
1
PARAMETER_SIGNED_DEC
USR
sld_attribute_mem_mode
OFF
PARAMETER_STRING
USR
 constraint(sld_ram_block_type)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_entity)
1 to 8
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_1)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_2)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_3)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_4)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_5)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_6)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_7)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_8)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_9)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_advanced_trigger_10)
1 to 4
PARAMETER_STRING
USR
 constraint(sld_inversion_mask)
0 to 23
PARAMETER_STRING
USR
 constraint(sld_state_flow_mgr_entity)
1 to 25
PARAMETER_STRING
USR
 constraint(sld_attribute_mem_mode)
1 to 3
PARAMETER_STRING
USR
 constraint(acq_data_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_in)
0 downto 0
PARAMETER_STRING
USR
 constraint(crc)
31 downto 0
PARAMETER_STRING
USR
 constraint(ir_in)
7 downto 0
PARAMETER_STRING
USR
 constraint(ir_out)
7 downto 0
PARAMETER_STRING
USR
 constraint(acq_data_out)
0 downto 0
PARAMETER_STRING
USR
 constraint(acq_trigger_out)
0 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|80|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
sld_ela_control
# storage
db|liid.(103).cnf
db|liid.(103).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|80|quartus|libraries|megafunctions|sld_ela_control.vhd
b8746f8c5081cfd95a504b53ff7071
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_input_width
1
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
trigger_in_enabled
0
PARAMETER_SIGNED_DEC
USR
advanced_trigger_entity
basic,1,
PARAMETER_STRING
USR
enable_advanced_trigger
0
PARAMETER_SIGNED_DEC
USR
trigger_level_pipeline
1
PARAMETER_SIGNED_DEC
USR
ela_status_bits
4
PARAMETER_SIGNED_DEC
USR
mem_address_bits
7
PARAMETER_SIGNED_DEC
USR
sample_depth
128
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PA