liid.tan.qmsg

利用fpga实现vga解码

{ "Info" "ITDB_FULL_TPD_RESULT" "we altera_auto_signaltap_0_we_a_from_arm~0_ae 10.229 ns Longest " "Info: Longest tpd from source pin \"we\" to destination pin \"altera_auto_signaltap_0_we_a_from_arm~0_ae\" is 10.229 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns we 1 PIN PIN_68 1 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_68; Fanout = 1; PIN Node = 'we'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { we } "NODE_NAME" } } { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.884 ns) + CELL(0.534 ns) 8.412 ns altera_auto_signaltap_0_we_a_from_arm~0_signaltap_lcell 2 COMB LCCOMB_X30_Y7_N20 5 " "Info: 2: + IC(6.884 ns) + CELL(0.534 ns) = 8.412 ns; Loc. = LCCOMB_X30_Y7_N20; Fanout = 5; COMB Node = 'altera_auto_signaltap_0_we_a_from_arm~0_signaltap_lcell'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.418 ns" { we altera_auto_signaltap_0_we_a_from_arm~0_signaltap_lcell } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.817 ns) + CELL(0.000 ns) 10.229 ns altera_auto_signaltap_0_we_a_from_arm~0_ae 3 PIN LCCOMB_X24_Y8_N10 0 " "Info: 3: + IC(1.817 ns) + CELL(0.000 ns) = 10.229 ns; Loc. = LCCOMB_X24_Y8_N10; Fanout = 0; PIN Node = 'altera_auto_signaltap_0_we_a_from_arm~0_ae'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.817 ns" { altera_auto_signaltap_0_we_a_from_arm~0_signaltap_lcell altera_auto_signaltap_0_we_a_from_arm~0_ae } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.528 ns ( 14.94 % ) " "Info: Total cell delay = 1.528 ns ( 14.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.701 ns ( 85.06 % ) " "Info: Total interconnect delay = 8.701 ns ( 85.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "10.229 ns" { we altera_auto_signaltap_0_we_a_from_arm~0_signaltap_lcell altera_auto_signaltap_0_we_a_from_arm~0_ae } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "10.229 ns" { we {} we~combout {} altera_auto_signaltap_0_we_a_from_arm~0_signaltap_lcell {} altera_auto_signaltap_0_we_a_from_arm~0_ae {} } { 0.000ns 0.000ns 6.884ns 1.817ns } { 0.000ns 0.994ns 0.534ns 0.000ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[5\] altera_internal_jtag~TMSUTAP altera_internal_jtag~TCKUTAP 2.119 ns register " "Info: th for register \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[5\]\" (data pin = \"altera_internal_jtag~TMSUTAP\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 2.119 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.376 ns + Longest register " "Info: + Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.376 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.825 ns) + CELL(0.000 ns) 3.825 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G1 313 " "Info: 2: + IC(3.825 ns) + CELL(0.000 ns) = 3.825 ns; Loc. = CLKCTRL_G1; Fanout = 313; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.825 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.885 ns) + CELL(0.666 ns) 5.376 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[5\] 3 REG LCFF_X21_Y11_N29 4 " "Info: 3: + IC(0.885 ns) + CELL(0.666 ns) = 5.376 ns; Loc. = LCFF_X21_Y11_N29; Fanout = 4; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[5\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.551 ns" { altera_i