liid.tan.qmsg

利用fpga实现vga解码

{ "Info" "ITDB_TSU_RESULT" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_data_in_reg\[28\] we clk 8.803 ns register " "Info: tsu for register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_data_in_reg\[28\]\" (data pin = \"we\", clock pin = \"clk\") is 8.803 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.677 ns + Longest pin register " "Info: + Longest pin to register delay is 11.677 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns we 1 PIN PIN_68 1 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_68; Fanout = 1; PIN Node = 'we'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { we } "NODE_NAME" } } { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.884 ns) + CELL(0.534 ns) 8.412 ns altera_auto_signaltap_0_we_a_from_arm~0_signaltap_lcell 2 COMB LCCOMB_X30_Y7_N20 5 " "Info: 2: + IC(6.884 ns) + CELL(0.534 ns) = 8.412 ns; Loc. = LCCOMB_X30_Y7_N20; Fanout = 5; COMB Node = 'altera_auto_signaltap_0_we_a_from_arm~0_signaltap_lcell'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.418 ns" { we altera_auto_signaltap_0_we_a_from_arm~0_signaltap_lcell } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.951 ns) + CELL(0.206 ns) 11.569 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_data_in_reg\[28\]~feeder 3 COMB LCCOMB_X16_Y9_N30 1 " "Info: 3: + IC(2.951 ns) + CELL(0.206 ns) = 11.569 ns; Loc. = LCCOMB_X16_Y9_N30; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_data_in_reg\[28\]~feeder'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.157 ns" { altera_auto_signaltap_0_we_a_from_arm~0_signaltap_lcell sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[28]~feeder } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" 948 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 11.677 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_data_in_reg\[28\] 4 REG LCFF_X16_Y9_N31 1 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 11.677 ns; Loc. = LCFF_X16_Y9_N31; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_data_in_reg\[28\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[28]~feeder sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[28] } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" 948 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.842 ns ( 15.77 % ) " "Info: Total cell delay = 1.842 ns ( 15.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.835 ns ( 84.23 % ) " "Info: Total interconnect delay = 9.835 ns ( 84.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "11.677 ns" { we altera_auto_signaltap_0_we_a_from_arm~0_signaltap_lcell sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[28]~feeder sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[28] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "11.677 ns" { we {} we~combout {} altera_auto_signaltap_0_we_a_from_arm~0_signaltap_lcell {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[28]~feeder {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[28] {} } { 0.000ns 0.000ns 6.884ns 2.951ns 0.000ns } { 0.000ns 0.994ns 0.534ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" 948 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.834 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.834 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 476 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 476; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.889 ns) + CELL(0.666 ns) 2.834 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_data_in_reg\[28\] 3 REG LCFF_X16_Y9_N31 1 " "Info: 3: + IC(0.889 ns) + CELL(0.666 ns) = 2.834 ns; Loc. = LCFF_X16_Y9_N31; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_data_in_reg\[28\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.555 ns" { clk~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[28] } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" 948 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.73 % ) " "Info: Total cell delay = 1.806 ns ( 63.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.028 ns ( 36.27 % ) " "Info: Total interconnect delay = 1.028 ns ( 36.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.834 ns" { clk clk~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[28] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.834 ns" { clk {} clk~combout {} clk~clkctrl {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[28] {} } { 0.000ns 0.000ns 0.139ns 0.889ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "11.677 ns" { we altera_auto_signaltap_0_we_a_from_arm~0_signaltap_lcell sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[28]~feeder sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[28] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "11.677 ns" { we {} we~combout {} altera_auto_signaltap_0_we_a_from_arm~0_signaltap_lcell {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[28]~feeder {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[28] {} } { 0.000ns 0.000ns 6.884ns 2.951ns 0.000ns } { 0.000ns 0.994ns 0.534ns 0.206ns 0.108ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.834 ns" { clk clk~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[28] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.834 ns" { clk {} clk~combout {} clk~clkctrl {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[28] {} } { 0.000ns 0.000ns 0.139ns 0.889ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk vga_r vga:vgak\|x_cnt\[3\] 15.689 ns register " "Info: tco from clock \"clk\" to destination pin \"vga_r\" through register \"vga:vgak\|x_cnt\[3\]\" is 15.689 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.873 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.873 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 476 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 476; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.928 ns) + CELL(0.666 ns) 2.873 ns vga:vgak\|x_cnt\[3\] 3 REG LCFF_X29_Y16_N13 6 " "Info: 3: + IC(0.928 ns) + CELL(0.666 ns) = 2.873 ns; Loc. = LCFF_X29_Y16_N13; Fanout = 6; REG Node = 'vga:vgak\|x_cnt\[3\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.594 ns" { clk~clkctrl vga:vgak|x_cnt[3] } "NODE_NAME" } } { "src/vga_ctr.v" "" { Text "D:/baby/lab_dream/Liid/src/vga_ctr.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 62.86 % ) " "Info: Total cell delay = 1.806 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.067 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.067 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.873 ns" { clk clk~clkctrl vga:vgak|x_cnt[3] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.873 ns" { clk {} clk~combout {} clk~clkctrl {} vga:vgak|x_cnt[3] {} } { 0.000ns 0.000ns 0.139ns 0.928ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "src/vga_ctr.v" "" { Text "D:/baby/lab_dream/Liid/src/vga_ctr.v" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.512 ns + Longest register pin " "Info: + Longest register to pin delay is 12.512 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga:vgak\|x_cnt\[3\] 1 REG LCFF_X29_Y16_N13 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y16_N13; Fanout = 6; REG Node = 'vga:vgak\|x_cnt\[3\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { vga:vgak|x_cnt[3] } "NODE_NAME" } } { "src/vga_ctr.v" "" { Text "D:/baby/lab_dream/Liid/src/vga_ctr.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.107 ns) + CELL(0.624 ns) 1.731 ns vga:vgak\|LessThan0~173 2 COMB LCCOMB_X31_Y16_N6 1 " "Info: 2: + IC(1.107 ns) + CELL(0.624 ns) = 1.731 ns; Loc. = LCCOMB_X31_Y16_N6; Fanout = 1; COMB Node = 'vga:vgak\|LessThan0~173'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.731 ns" { vga:vgak|x_cnt[3] vga:vgak|LessThan0~173 } "NODE_NAME" } } { "src/vga_ctr.v" "" { Text "D:/baby/lab_dream/Liid/src/vga_ctr.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.382 ns) + CELL(0.206 ns) 2.319 ns vga:vgak\|LessThan0~170 3 COMB LCCOMB_X31_Y16_N4 1 " "Info: 3: + IC(0.382 ns) + CELL(0.206 ns) = 2.319 ns; Loc. = LCCOMB_X31_Y16_N4; Fanout = 1; COMB Node = 'vga:vgak\|LessThan0~170'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.588 ns" { vga:vgak|LessThan0~173 vga:vgak|LessThan0~170 } "NODE_NAME" } } { "src/vga_ctr.v" "" { Text "D:/baby/lab_dream/Liid/src/vga_ctr.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.024 ns) + CELL(0.366 ns) 3.709 ns vga:vgak\|LessThan0~189 4 COMB LCCOMB_X29_Y16_N30 1 " "Info: 4: + IC(1.024 ns) + CELL(0.366 ns) = 3.709 ns; Loc. = LCCOMB_X29_Y16_N30; Fanout = 1; COMB Node = 'vga:vgak\|LessThan0~189'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.390 ns" { vga:vgak|LessThan0~170 vga:vgak|LessThan0~189 } "NODE_NAME" } } { "src/vga_ctr.v" "" { Text "D:/baby/lab_dream/Liid/src/vga_ctr.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.366 ns) + CELL(0.624 ns) 4.699 ns vga:vgak\|Rgb_valid~46 5 COMB LCCOMB_X29_Y16_N22 3 " "Info: 5: + IC(0.366 ns) + CELL(0.624 ns) = 4.699 ns; Loc. = LCCOMB_X29_Y16_N22; Fanout = 3; COMB Node = 'vga:vgak\|Rgb_valid~46'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.990 ns" { vga:vgak|LessThan0~189 vga:vgak|Rgb_valid~46 } "NODE_NAME" } } { "src/vga_ctr.v" "" { Text "D:/baby/lab_dream/Liid/src/vga_ctr.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.947 ns) + CELL(0.589 ns) 7.235 ns vga:vgak\|vga_r~10 6 COMB LCCOMB_X26_Y8_N30 1 " "Info: 6: + IC(1.947 ns) + CELL(0.589 ns) = 7.235 ns; Loc. = LCCOMB_X26_Y8_N30; Fanout = 1; COMB Node = 'vga:vgak\|vga_r~10'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.536 ns" { vga:vgak|Rgb_valid~46 vga:vgak|vga_r~10 } "NODE_NAME" } } { "src/vga_ctr.v" "" { Text "D:/baby/lab_dream/Liid/src/vga_ctr.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.191 ns) + CELL(3.086 ns) 12.512 ns vga_r 7 PIN PIN_112 0 " "Info: 7: + IC(2.191 ns) + CELL(3.086 ns) = 12.512 ns; Loc. = PIN_112; Fanout = 0; PIN Node = 'vga_r'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.277 ns" { vga:vgak|vga_r~10 vga_r } "NODE_NAME" } } { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.495 ns ( 43.92 % ) " "Info: Total cell delay = 5.495 ns ( 43.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.017 ns ( 56.08 % ) " "Info: Total interconnect delay = 7.017 ns ( 56.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "12.512 ns" { vga:vgak|x_cnt[3] vga:vgak|LessThan0~173 vga:vgak|LessThan0~170 vga:vgak|LessThan0~189 vga:vgak|Rgb_valid~46 vga:vgak|vga_r~10 vga_r } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "12.512 ns" { vga:vgak|x_cnt[3] {} vga:vgak|LessThan0~173 {} vga:vgak|LessThan0~170 {} vga:vgak|LessThan0~189 {} vga:vgak|Rgb_valid~46 {} vga:vgak|vga_r~10 {} vga_r {} } { 0.000ns 1.107ns 0.382ns 1.024ns 0.366ns 1.947ns 2.191ns } { 0.000ns 0.624ns 0.206ns 0.366ns 0.624ns 0.589ns 3.086ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.873 ns" { clk clk~clkctrl vga:vgak|x_cnt[3] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.873 ns" { clk {} clk~combout {} clk~clkctrl {} vga:vgak|x_cnt[3] {} } { 0.000ns 0.000ns 0.139ns 0.928ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "12.512 ns" { vga:vgak|x_cnt[3] vga:vgak|LessThan0~173 vga:vgak|LessThan0~170 vga:vgak|LessThan0~189 vga:vgak|Rgb_valid~46 vga:vgak|vga_r~10 vga_r } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "12.512 ns" { vga:vgak|x_cnt[3] {} vga:vgak|LessThan0~173 {} vga:vgak|LessThan0~170 {} vga:vgak|LessThan0~189 {} vga:vgak|Rgb_valid~46 {} vga:vgak|vga_r~10 {} vga_r {} } { 0.000ns 1.107ns 0.382ns 1.024ns 0.366ns 1.947ns 2.191ns } { 0.000ns 0.624ns 0.206ns 0.366ns 0.624ns 0.589ns 3.086ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}