📄 liid.tan.qmsg

📁 利用fpga实现vga解码
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register addr_b_inc\[18\] memory video_buffer:video_bufferk\|altsyncram:ram__dual_rtl_0\|altsyncram_jpi1:auto_generated\|ram_block1a0~portb_address_reg0 151.4 MHz 6.605 ns Internal " "Info: Clock \"clk\" has Internal fmax of 151.4 MHz between source register \"addr_b_inc\[18\]\" and destination memory \"video_buffer:video_bufferk\|altsyncram:ram__dual_rtl_0\|altsyncram_jpi1:auto_generated\|ram_block1a0~portb_address_reg0\" (period= 6.605 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.381 ns + Longest register memory " "Info: + Longest register to memory delay is 6.381 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns addr_b_inc\[18\] 1 REG LCFF_X28_Y7_N23 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X28_Y7_N23; Fanout = 3; REG Node = 'addr_b_inc\[18\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { addr_b_inc[18] } "NODE_NAME" } } { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.178 ns) + CELL(0.651 ns) 1.829 ns LessThan0~523 2 COMB LCCOMB_X28_Y8_N30 1 " "Info: 2: + IC(1.178 ns) + CELL(0.651 ns) = 1.829 ns; Loc. = LCCOMB_X28_Y8_N30; Fanout = 1; COMB Node = 'LessThan0~523'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.829 ns" { addr_b_inc[18] LessThan0~523 } "NODE_NAME" } } { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.366 ns) + CELL(0.624 ns) 2.819 ns LessThan0~525 3 COMB LCCOMB_X28_Y8_N26 1 " "Info: 3: + IC(0.366 ns) + CELL(0.624 ns) = 2.819 ns; Loc. = LCCOMB_X28_Y8_N26; Fanout = 1; COMB Node = 'LessThan0~525'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.990 ns" { LessThan0~523 LessThan0~525 } "NODE_NAME" } } { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.361 ns) + CELL(0.206 ns) 3.386 ns LessThan0~526 4 COMB LCCOMB_X28_Y8_N4 1 " "Info: 4: + IC(0.361 ns) + CELL(0.206 ns) = 3.386 ns; Loc. = LCCOMB_X28_Y8_N4; Fanout = 1; COMB Node = 'LessThan0~526'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.567 ns" { LessThan0~525 LessThan0~526 } "NODE_NAME" } } { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.364 ns) + CELL(0.624 ns) 4.374 ns LessThan0~528 5 COMB LCCOMB_X28_Y8_N6 32 " "Info: 5: + IC(0.364 ns) + CELL(0.624 ns) = 4.374 ns; Loc. = LCCOMB_X28_Y8_N6; Fanout = 32; COMB Node = 'LessThan0~528'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.988 ns" { LessThan0~526 LessThan0~528 } "NODE_NAME" } } { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.202 ns) 5.013 ns Add0~1650 6 COMB LCCOMB_X28_Y8_N24 2 " "Info: 6: + IC(0.437 ns) + CELL(0.202 ns) = 5.013 ns; Loc. = LCCOMB_X28_Y8_N24; Fanout = 2; COMB Node = 'Add0~1650'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.639 ns" { LessThan0~528 Add0~1650 } "NODE_NAME" } } { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.192 ns) + CELL(0.176 ns) 6.381 ns video_buffer:video_bufferk\|altsyncram:ram__dual_rtl_0\|altsyncram_jpi1:auto_generated\|ram_block1a0~portb_address_reg0 7 MEM M4K_X27_Y8 4 " "Info: 7: + IC(1.192 ns) + CELL(0.176 ns) = 6.381 ns; Loc. = M4K_X27_Y8; Fanout = 4; MEM Node = 'video_buffer:video_bufferk\|altsyncram:ram__dual_rtl_0\|altsyncram_jpi1:auto_generated\|ram_block1a0~portb_address_reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.368 ns" { Add0~1650 video_buffer:video_bufferk|altsyncram:ram__dual_rtl_0|altsyncram_jpi1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_jpi1.tdf" "" { Text "D:/baby/lab_dream/Liid/db/altsyncram_jpi1.tdf" 37 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.483 ns ( 38.91 % ) " "Info: Total cell delay = 2.483 ns ( 38.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.898 ns ( 61.09 % ) " "Info: Total interconnect delay = 3.898 ns ( 61.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.381 ns" { addr_b_inc[18] LessThan0~523 LessThan0~525 LessThan0~526 LessThan0~528 Add0~1650 video_buffer:video_bufferk|altsyncram:ram__dual_rtl_0|altsyncram_jpi1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.381 ns" { addr_b_inc[18] {} LessThan0~523 {} LessThan0~525 {} LessThan0~526 {} LessThan0~528 {} Add0~1650 {} video_buffer:video_bufferk|altsyncram:ram__dual_rtl_0|altsyncram_jpi1:auto_generated|ram_block1a0~portb_address_reg0 {} } { 0.000ns 1.178ns 0.366ns 0.361ns 0.364ns 0.437ns 1.192ns } { 0.000ns 0.651ns 0.624ns 0.206ns 0.624ns 0.202ns 0.176ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.126 ns - Smallest " "Info: - Smallest clock skew is 0.126 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.979 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk\" to destination memory is 2.979 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 476 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 476; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.822 ns) + CELL(0.878 ns) 2.979 ns video_buffer:video_bufferk\|altsyncram:ram__dual_rtl_0\|altsyncram_jpi1:auto_generated\|ram_block1a0~portb_address_reg0 3 MEM M4K_X27_Y8 4 " "Info: 3: + IC(0.822 ns) + CELL(0.878 ns) = 2.979 ns; Loc. = M4K_X27_Y8; Fanout = 4; MEM Node = 'video_buffer:video_bufferk\|altsyncram:ram__dual_rtl_0\|altsyncram_jpi1:auto_generated\|ram_block1a0~portb_address_reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { clk~clkctrl video_buffer:video_bufferk|altsyncram:ram__dual_rtl_0|altsyncram_jpi1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_jpi1.tdf" "" { Text "D:/baby/lab_dream/Liid/db/altsyncram_jpi1.tdf" 37 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.018 ns ( 67.74 % ) " "Info: Total cell delay = 2.018 ns ( 67.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.961 ns ( 32.26 % ) " "Info: Total interconnect delay = 0.961 ns ( 32.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.979 ns" { clk clk~clkctrl video_buffer:video_bufferk|altsyncram:ram__dual_rtl_0|altsyncram_jpi1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.979 ns" { clk {} clk~combout {} clk~clkctrl {} video_buffer:video_bufferk|altsyncram:ram__dual_rtl_0|altsyncram_jpi1:auto_generated|ram_block1a0~portb_address_reg0 {} } { 0.000ns 0.000ns 0.139ns 0.822ns } { 0.000ns 1.140ns 0.000ns 0.878ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.853 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.853 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk~clkctrl 2 COMB CLKCTRL_G2 476 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 476; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk clk~clkctrl } "NODE_NAME" } } { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.908 ns) + CELL(0.666 ns) 2.853 ns addr_b_inc\[18\] 3 REG LCFF_X28_Y7_N23 3 " "Info: 3: + IC(0.908 ns) + CELL(0.666 ns) = 2.853 ns; Loc. = LCFF_X28_Y7_N23; Fanout = 3; REG Node = 'addr_b_inc\[18\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.574 ns" { clk~clkctrl addr_b_inc[18] } "NODE_NAME" } } { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.30 % ) " "Info: Total cell delay = 1.806 ns ( 63.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.047 ns ( 36.70 % ) " "Info: Total interconnect delay = 1.047 ns ( 36.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { clk clk~clkctrl addr_b_inc[18] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { clk {} clk~combout {} clk~clkctrl {} addr_b_inc[18] {} } { 0.000ns 0.000ns 0.139ns 0.908ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.979 ns" { clk clk~clkctrl video_buffer:video_bufferk|altsyncram:ram__dual_rtl_0|altsyncram_jpi1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.979 ns" { clk {} clk~combout {} clk~clkctrl {} video_buffer:video_bufferk|altsyncram:ram__dual_rtl_0|altsyncram_jpi1:auto_generated|ram_block1a0~portb_address_reg0 {} } { 0.000ns 0.000ns 0.139ns 0.822ns } { 0.000ns 1.140ns 0.000ns 0.878ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { clk clk~clkctrl addr_b_inc[18] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { clk {} clk~combout {} clk~clkctrl {} addr_b_inc[18] {} } { 0.000ns 0.000ns 0.139ns 0.908ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 84 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_jpi1.tdf" "" { Text "D:/baby/lab_dream/Liid/db/altsyncram_jpi1.tdf" 37 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.381 ns" { addr_b_inc[18] LessThan0~523 LessThan0~525 LessThan0~526 LessThan0~528 Add0~1650 video_buffer:video_bufferk|altsyncram:ram__dual_rtl_0|altsyncram_jpi1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.381 ns" { addr_b_inc[18] {} LessThan0~523 {} LessThan0~525 {} LessThan0~526 {} LessThan0~528 {} Add0~1650 {} video_buffer:video_bufferk|altsyncram:ram__dual_rtl_0|altsyncram_jpi1:auto_generated|ram_block1a0~portb_address_reg0 {} } { 0.000ns 1.178ns 0.366ns 0.361ns 0.364ns 0.437ns 1.192ns } { 0.000ns 0.651ns 0.624ns 0.206ns 0.624ns 0.202ns 0.176ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.979 ns" { clk clk~clkctrl video_buffer:video_bufferk|altsyncram:ram__dual_rtl_0|altsyncram_jpi1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.979 ns" { clk {} clk~combout {} clk~clkctrl {} video_buffer:video_bufferk|altsyncram:ram__dual_rtl_0|altsyncram_jpi1:auto_generated|ram_block1a0~portb_address_reg0 {} } { 0.000ns 0.000ns 0.139ns 0.822ns } { 0.000ns 1.140ns 0.000ns 0.878ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.853 ns" { clk clk~clkctrl addr_b_inc[18] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.853 ns" { clk {} clk~combout {} clk~clkctrl {} addr_b_inc[18] {} } { 0.000ns 0.000ns 0.139ns 0.908ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] register sld_hub:sld_hub_inst\|hub_tdo_reg 98.0 MHz 10.204 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 98.0 MHz between source register \"sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo_reg\" (period= 10.204 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.838 ns + Longest register register " "Info: + Longest register to register delay is 4.838 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] 1 REG LCFF_X23_Y11_N3 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X23_Y11_N3; Fanout = 12; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.442 ns) + CELL(0.505 ns) 0.947 ns sld_hub:sld_hub_inst\|node_ena~10 2 COMB LCCOMB_X23_Y11_N24 5 " "Info: 2: + IC(0.442 ns) + CELL(0.505 ns) = 0.947 ns; Loc. = LCCOMB_X23_Y11_N24; Fanout = 5; COMB Node = 'sld_hub:sld_hub_inst\|node_ena~10'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.947 ns" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] sld_hub:sld_hub_inst|node_ena~10 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" 136 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.698 ns) + CELL(0.206 ns) 1.851 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|crc_rom_sr_ena~32 3 COMB LCCOMB_X22_Y11_N2 5 " "Info: 3: + IC(0.698 ns) + CELL(0.206 ns) = 1.851 ns; Loc. = LCCOMB_X22_Y11_N2; Fanout = 5; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|crc_rom_sr_ena~32'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.904 ns" { sld_hub:sld_hub_inst|node_ena~10 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~32 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" 806 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.390 ns) + CELL(0.206 ns) 2.447 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|status_shift_enable~58 4 COMB LCCOMB_X22_Y11_N12 18 " "Info: 4: + IC(0.390 ns) + CELL(0.206 ns) = 2.447 ns; Loc. = LCCOMB_X22_Y11_N12; Fanout = 18; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|status_shift_enable~58'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.596 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~32 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~58 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" 834 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.362 ns) + CELL(0.206 ns) 3.015 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~442 5 COMB LCCOMB_X22_Y11_N22 1 " "Info: 5: + IC(0.362 ns) + CELL(0.206 ns) = 3.015 ns; Loc. = LCCOMB_X22_Y11_N22; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~442'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.568 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~58 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~442 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" 518 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.373 ns) + CELL(0.206 ns) 3.594 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~445 6 COMB LCCOMB_X22_Y11_N28 1 " "Info: 6: + IC(0.373 ns) + CELL(0.206 ns) = 3.594 ns; Loc. = LCCOMB_X22_Y11_N28; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~445'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.579 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~442 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~445 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" 518 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.361 ns) + CELL(0.206 ns) 4.161 ns sld_hub:sld_hub_inst\|hub_tdo_reg~294 7 COMB LCCOMB_X22_Y11_N0 1 " "Info: 7: + IC(0.361 ns) + CELL(0.206 ns) = 4.161 ns; Loc. = LCCOMB_X22_Y11_N0; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~294'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.567 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~445 sld_hub:sld_hub_inst|hub_tdo_reg~294 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.363 ns) + CELL(0.206 ns) 4.730 ns sld_hub:sld_hub_inst\|hub_tdo_reg~295 8 COMB LCCOMB_X22_Y11_N20 1 " "Info: 8: + IC(0.363 ns) + CELL(0.206 ns) = 4.730 ns; Loc. = LCCOMB_X22_Y11_N20; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~295'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.569 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~294 sld_hub:sld_hub_inst|hub_tdo_reg~295 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 4.838 ns sld_hub:sld_hub_inst\|hub_tdo_reg 9 REG LCFF_X22_Y11_N21 2 " "Info: 9: + IC(0.000 ns) + CELL(0.108 ns) = 4.838 ns; Loc. = LCFF_X22_Y11_N21; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~295 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.849 ns ( 38.22 % ) " "Info: Total cell delay = 1.849 ns ( 38.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.989 ns ( 61.78 % ) " "Info: Total interconnect delay = 2.989 ns ( 61.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.838 ns" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] sld_hub:sld_hub_inst|node_ena~10 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~32 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~58 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~442 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~445 sld_hub:sld_hub_inst|hub_tdo_reg~294 sld_hub:sld_hub_inst|hub_tdo_reg~295 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.838 ns" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] {} sld_hub:sld_hub_inst|node_ena~10 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~32 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~58 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~442 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~445 {} sld_hub:sld_hub_inst|hub_tdo_reg~294 {} sld_hub:sld_hub_inst|hub_tdo_reg~295 {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 0.442ns 0.698ns 0.390ns 0.362ns 0.373ns 0.361ns 0.363ns 0.000ns } { 0.000ns 0.505ns 0.206ns 0.206ns 0.206ns 0.206ns 0.206ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.378 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.378 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.825 ns) + CELL(0.000 ns) 3.825 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G1 313 " "Info: 2: + IC(3.825 ns) + CELL(0.000 ns) = 3.825 ns; Loc. = CLKCTRL_G1; Fanout = 313; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.825 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.887 ns) + CELL(0.666 ns) 5.378 ns sld_hub:sld_hub_inst\|hub_tdo_reg 3 REG LCFF_X22_Y11_N21 2 " "Info: 3: + IC(0.887 ns) + CELL(0.666 ns) = 5.378 ns; Loc. = LCFF_X22_Y11_N21; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.553 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 12.38 % ) " "Info: Total cell delay = 0.666 ns ( 12.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.712 ns ( 87.62 % ) " "Info: Total interconnect delay = 4.712 ns ( 87.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.378 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.378 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 3.825ns 0.887ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.378 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.378 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.825 ns) + CELL(0.000 ns) 3.825 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G1 313 " "Info: 2: + IC(3.825 ns) + CELL(0.000 ns) = 3.825 ns; Loc. = CLKCTRL_G1; Fanout = 313; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.825 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.887 ns) + CELL(0.666 ns) 5.378 ns sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] 3 REG LCFF_X23_Y11_N3 12 " "Info: 3: + IC(0.887 ns) + CELL(0.666 ns) = 5.378 ns; Loc. = LCFF_X23_Y11_N3; Fanout = 12; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.553 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 12.38 % ) " "Info: Total cell delay = 0.666 ns ( 12.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.712 ns ( 87.62 % ) " "Info: Total interconnect delay = 4.712 ns ( 87.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.378 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.378 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] {} } { 0.000ns 3.825ns 0.887ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.378 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.378 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 3.825ns 0.887ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.378 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.378 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] {} } { 0.000ns 3.825ns 0.887ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "c:/altera/80/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "c:/altera/80/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.838 ns" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] sld_hub:sld_hub_inst|node_ena~10 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~32 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~58 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~442 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~445 sld_hub:sld_hub_inst|hub_tdo_reg~294 sld_hub:sld_hub_inst|hub_tdo_reg~295 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.838 ns" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] {} sld_hub:sld_hub_inst|node_ena~10 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~32 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~58 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~442 {} sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~445 {} sld_hub:sld_hub_inst|hub_tdo_reg~294 {} sld_hub:sld_hub_inst|hub_tdo_reg~295 {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 0.442ns 0.698ns 0.390ns 0.362ns 0.373ns 0.361ns 0.363ns 0.000ns } { 0.000ns 0.505ns 0.206ns 0.206ns 0.206ns 0.206ns 0.206ns 0.206ns 0.108ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.378 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.378 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|hub_tdo_reg {} } { 0.000ns 3.825ns 0.887ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.378 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.378 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] {} } { 0.000ns 3.825ns 0.887ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
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