mux_3mb.tdf

利用fpga实现vga解码

--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_SIZE=193 LPM_WIDTH=8 LPM_WIDTHS=8 data result sel
--VERSION_BEGIN 8.0 cbx_lpm_mux 2008:02:23:252825 cbx_mgl 2008:04:11:273944  VERSION_END


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--  without limitation, that your use is for the sole purpose of 
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--  applicable agreement for further details.



--synthesis_resources = lut 1360 
SUBDESIGN mux_3mb
( 
	data[1543..0]	:	input;
	result[7..0]	:	output;
	sel[7..0]	:	input;
) 
VARIABLE 
	result_node[7..0]	: WIRE;
	sel_ffs_wire[23..0]	: WIRE;
	sel_node[7..0]	: WIRE;
	w_data15836w[255..0]	: WIRE;
	w_data16262w[3..0]	: WIRE;
	w_data16263w[3..0]	: WIRE;
	w_data16264w[3..0]	: WIRE;
	w_data16265w[3..0]	: WIRE;
	w_data16365w[3..0]	: WIRE;
	w_data16366w[3..0]	: WIRE;
	w_data16367w[3..0]	: WIRE;
	w_data16368w[3..0]	: WIRE;
	w_data16463w[3..0]	: WIRE;
	w_data16464w[3..0]	: WIRE;
	w_data16465w[3..0]	: WIRE;
	w_data16466w[3..0]	: WIRE;
	w_data16561w[3..0]	: WIRE;
	w_data16562w[3..0]	: WIRE;
	w_data16563w[3..0]	: WIRE;
	w_data16564w[3..0]	: WIRE;
	w_data16689w[3..0]	: WIRE;
	w_data16690w[3..0]	: WIRE;
	w_data16691w[3..0]	: WIRE;
	w_data16692w[3..0]	: WIRE;
	w_data16792w[3..0]	: WIRE;
	w_data16793w[3..0]	: WIRE;
	w_data16794w[3..0]	: WIRE;
	w_data16795w[3..0]	: WIRE;
	w_data16890w[3..0]	: WIRE;
	w_data16891w[3..0]	: WIRE;
	w_data16892w[3..0]	: WIRE;
	w_data16893w[3..0]	: WIRE;
	w_data16988w[3..0]	: WIRE;
	w_data16989w[3..0]	: WIRE;
	w_data16990w[3..0]	: WIRE;
	w_data16991w[3..0]	: WIRE;
	w_data17112w[3..0]	: WIRE;
	w_data17113w[3..0]	: WIRE;
	w_data17114w[3..0]	: WIRE;
	w_data17115w[3..0]	: WIRE;
	w_data17215w[3..0]	: WIRE;
	w_data17216w[3..0]	: WIRE;
	w_data17217w[3..0]	: WIRE;
	w_data17218w[3..0]	: WIRE;
	w_data17313w[3..0]	: WIRE;
	w_data17314w[3..0]	: WIRE;
	w_data17315w[3..0]	: WIRE;
	w_data17316w[3..0]	: WIRE;
	w_data17411w[3..0]	: WIRE;
	w_data17412w[3..0]	: WIRE;
	w_data17413w[3..0]	: WIRE;
	w_data17414w[3..0]	: WIRE;
	w_data17535w[3..0]	: WIRE;
	w_data17536w[3..0]	: WIRE;
	w_data17537w[3..0]	: WIRE;
	w_data17538w[3..0]	: WIRE;
	w_data17638w[3..0]	: WIRE;
	w_data17639w[3..0]	: WIRE;
	w_data17640w[3..0]	: WIRE;
	w_data17641w[3..0]	: WIRE;
	w_data17736w[3..0]	: WIRE;
	w_data17737w[3..0]	: WIRE;
	w_data17738w[3..0]	: WIRE;
	w_data17739w[3..0]	: WIRE;
	w_data17834w[3..0]	: WIRE;
	w_data17835w[3..0]	: WIRE;
	w_data17836w[3..0]	: WIRE;
	w_data17837w[3..0]	: WIRE;
	w_data17957w[255..0]	: WIRE;
	w_data18382w[3..0]	: WIRE;
	w_data18383w[3..0]	: WIRE;
	w_data18384w[3..0]	: WIRE;
	w_data18385w[3..0]	: WIRE;
	w_data18485w[3..0]	: WIRE;
	w_data18486w[3..0]	: WIRE;
	w_data18487w[3..0]	: WIRE;
	w_data18488w[3..0]	: WIRE;
	w_data18583w[3..0]	: WIRE;
	w_data18584w[3..0]	: WIRE;
	w_data18585w[3..0]	: WIRE;
	w_data18586w[3..0]	: WIRE;
	w_data18681w[3..0]	: WIRE;
	w_data18682w[3..0]	: WIRE;
	w_data18683w[3..0]	: WIRE;
	w_data18684w[3..0]	: WIRE;
	w_data18809w[3..0]	: WIRE;
	w_data18810w[3..0]	: WIRE;
	w_data18811w[3..0]	: WIRE;
	w_data18812w[3..0]	: WIRE;
	w_data18912w[3..0]	: WIRE;
	w_data18913w[3..0]	: WIRE;
	w_data18914w[3..0]	: WIRE;
	w_data18915w[3..0]	: WIRE;
	w_data19010w[3..0]	: WIRE;
	w_data19011w[3..0]	: WIRE;
	w_data19012w[3..0]	: WIRE;
	w_data19013w[3..0]	: WIRE;
	w_data19108w[3..0]	: WIRE;
	w_data19109w[3..0]	: WIRE;
	w_data19110w[3..0]	: WIRE;
	w_data19111w[3..0]	: WIRE;
	w_data19232w[3..0]	: WIRE;
	w_data19233w[3..0]	: WIRE;
	w_data19234w[3..0]	: WIRE;
	w_data19235w[3..0]	: WIRE;
	w_data19335w[3..0]	: WIRE;
	w_data19336w[3..0]	: WIRE;
	w_data19337w[3..0]	: WIRE;
	w_data19338w[3..0]	: WIRE;
	w_data19433w[3..0]	: WIRE;
	w_data19434w[3..0]	: WIRE;
	w_data19435w[3..0]	: WIRE;
	w_data19436w[3..0]	: WIRE;
	w_data19531w[3..0]	: WIRE;
	w_data19532w[3..0]	: WIRE;
	w_data19533w[3..0]	: WIRE;
	w_data19534w[3..0]	: WIRE;