prev_cmp_liid.fit.qmsg

利用fpga实现vga解码

{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.107 ns register register " "Info: Estimated most critical path is register to register delay of 6.107 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|jtag_debug_mode 1 REG LAB_X28_Y14 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X28_Y14; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" 394 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.230 ns) + CELL(0.650 ns) 0.880 ns sld_hub:sld_hub_inst\|node_ena~10 2 COMB LAB_X28_Y14 5 " "Info: 2: + IC(0.230 ns) + CELL(0.650 ns) = 0.880 ns; Loc. = LAB_X28_Y14; Fanout = 5; COMB Node = 'sld_hub:sld_hub_inst\|node_ena~10'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.880 ns" { sld_hub:sld_hub_inst|jtag_debug_mode sld_hub:sld_hub_inst|node_ena~10 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" 136 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.466 ns) + CELL(0.651 ns) 1.997 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|crc_rom_sr_ena~32 3 COMB LAB_X29_Y14 5 " "Info: 3: + IC(0.466 ns) + CELL(0.651 ns) = 1.997 ns; Loc. = LAB_X29_Y14; Fanout = 5; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|crc_rom_sr_ena~32'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.117 ns" { sld_hub:sld_hub_inst|node_ena~10 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~32 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" 806 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.160 ns) + CELL(0.651 ns) 2.808 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|status_shift_enable~58 4 COMB LAB_X29_Y14 18 " "Info: 4: + IC(0.160 ns) + CELL(0.651 ns) = 2.808 ns; Loc. = LAB_X29_Y14; Fanout = 18; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|status_shift_enable~58'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~32 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~58 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" 834 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.605 ns) + CELL(0.206 ns) 3.619 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~442 5 COMB LAB_X29_Y14 1 " "Info: 5: + IC(0.605 ns) + CELL(0.206 ns) = 3.619 ns; Loc. = LAB_X29_Y14; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~442'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~58 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~442 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" 518 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.160 ns) + CELL(0.651 ns) 4.430 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~445 6 COMB LAB_X29_Y14 1 " "Info: 6: + IC(0.160 ns) + CELL(0.651 ns) = 4.430 ns; Loc. = LAB_X29_Y14; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~445'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~442 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~445 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" 518 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.441 ns) + CELL(0.370 ns) 5.241 ns sld_hub:sld_hub_inst\|hub_tdo_reg~294 7 COMB LAB_X29_Y14 1 " "Info: 7: + IC(0.441 ns) + CELL(0.370 ns) = 5.241 ns; Loc. = LAB_X29_Y14; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~294'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~445 sld_hub:sld_hub_inst|hub_tdo_reg~294 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.187 ns) + CELL(0.571 ns) 5.999 ns sld_hub:sld_hub_inst\|hub_tdo_reg~295 8 COMB LAB_X29_Y14 1 " "Info: 8: + IC(0.187 ns) + CELL(0.571 ns) = 5.999 ns; Loc. = LAB_X29_Y14; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~295'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.758 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~294 sld_hub:sld_hub_inst|hub_tdo_reg~295 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.107 ns sld_hub:sld_hub_inst\|hub_tdo_reg 9 REG LAB_X29_Y14 2 " "Info: 9: + IC(0.000 ns) + CELL(0.108 ns) = 6.107 ns; Loc. = LAB_X29_Y14; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~295 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.858 ns ( 63.17 % ) " "Info: Total cell delay = 3.858 ns ( 63.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.249 ns ( 36.83 % ) " "Info: Total interconnect delay = 2.249 ns ( 36.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.107 ns" { sld_hub:sld_hub_inst|jtag_debug_mode sld_hub:sld_hub_inst|node_ena~10 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~32 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~58 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~442 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~445 sld_hub:sld_hub_inst|hub_tdo_reg~294 sld_hub:sld_hub_inst|hub_tdo_reg~295 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Average interconnect usage is 1% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "5 X23_Y0 X34_Y9 " "Info: Peak interconnect usage is 5% of the available device resources in the region that extends from location X23_Y0 to location X34_Y9" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Info: Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "6 " "Warning: Found 6 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hsync 0 " "Info: Pin \"hsync\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "vsync 0 " "Info: Pin \"vsync\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "vga_r 0 " "Info: Pin \"vga_r\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "vga_g 0 " "Info: Pin \"vga_g\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "vga_b 0 " "Info: Pin \"vga_b\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "high 0 " "Info: Pin \"high\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "high VCC " "Info: Pin high has VCC driving its datain port" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { high } } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "high" } } } } { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 22 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { high } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/baby/lab_dream/Liid/liid.fit.smsg " "Info: Generated suppressed messages file D:/baby/lab_dream/Liid/liid.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "194 " "Info: Peak virtual memory: 194 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 23 22:16:17 2009 " "Info: Processing ended: Thu Apr 23 22:16:17 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:30 " "Info: Elapsed time: 00:00:30" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:20 " "Info: Total CPU time (on all processors): 00:00:20" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}