mux_llb.tdf

利用fpga实现vga解码

--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_SIZE=32 LPM_WIDTH=23 LPM_WIDTHS=5 data result sel
--VERSION_BEGIN 8.0 cbx_lpm_mux 2008:02:23:252825 cbx_mgl 2008:04:11:273944  VERSION_END


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--synthesis_resources = lut 483 
SUBDESIGN mux_llb
( 
	data[735..0]	:	input;
	result[22..0]	:	output;
	sel[4..0]	:	input;
) 
VARIABLE 
	result_node[22..0]	: WIRE;
	sel_ffs_wire[9..0]	: WIRE;
	sel_node[4..0]	: WIRE;
	w_data10000w[3..0]	: WIRE;
	w_data10001w[3..0]	: WIRE;
	w_data10095w[31..0]	: WIRE;
	w_data10175w[3..0]	: WIRE;
	w_data10176w[3..0]	: WIRE;
	w_data10177w[3..0]	: WIRE;
	w_data10178w[3..0]	: WIRE;
	w_data10278w[3..0]	: WIRE;
	w_data10279w[3..0]	: WIRE;
	w_data10280w[3..0]	: WIRE;
	w_data10281w[3..0]	: WIRE;
	w_data10375w[31..0]	: WIRE;
	w_data10455w[3..0]	: WIRE;
	w_data10456w[3..0]	: WIRE;
	w_data10457w[3..0]	: WIRE;
	w_data10458w[3..0]	: WIRE;
	w_data10558w[3..0]	: WIRE;
	w_data10559w[3..0]	: WIRE;
	w_data10560w[3..0]	: WIRE;
	w_data10561w[3..0]	: WIRE;
	w_data10655w[31..0]	: WIRE;
	w_data10735w[3..0]	: WIRE;
	w_data10736w[3..0]	: WIRE;
	w_data10737w[3..0]	: WIRE;
	w_data10738w[3..0]	: WIRE;
	w_data10838w[3..0]	: WIRE;
	w_data10839w[3..0]	: WIRE;
	w_data10840w[3..0]	: WIRE;
	w_data10841w[3..0]	: WIRE;
	w_data10935w[31..0]	: WIRE;
	w_data11015w[3..0]	: WIRE;
	w_data11016w[3..0]	: WIRE;