prev_cmp_liid.map.qmsg

利用fpga实现vga解码

{ "Info" "ISGN_MEGAFN_PARAM_TOP" "video_buffer:video_bufferk\|altsyncram:ram__dual_rtl_0 " "Info: Instantiated megafunction \"video_buffer:video_bufferk\|altsyncram:ram__dual_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Info: Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 4 " "Info: Parameter \"WIDTH_A\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 8 " "Info: Parameter \"WIDTHAD_A\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 129 " "Info: Parameter \"NUMWORDS_A\" = \"129\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 4 " "Info: Parameter \"WIDTH_B\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 8 " "Info: Parameter \"WIDTHAD_B\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 129 " "Info: Parameter \"NUMWORDS_B\" = \"129\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Info: Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B UNREGISTERED " "Info: Parameter \"OUTDATA_REG_B\" = \"UNREGISTERED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Info: Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Info: Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK1 " "Info: Parameter \"ADDRESS_REG_B\" = \"CLOCK1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Info: Parameter \"INDATA_ACLR_A\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Info: Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "RAM_BLOCK_TYPE AUTO " "Info: Parameter \"RAM_BLOCK_TYPE\" = \"AUTO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_pse1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_pse1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_pse1 " "Info: Found entity 1: altsyncram_pse1" {  } { { "db/altsyncram_pse1.tdf" "" { Text "D:/baby/lab_dream/Liid/db/altsyncram_pse1.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_sfi1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_sfi1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_sfi1 " "Info: Found entity 1: altsyncram_sfi1" {  } { { "db/altsyncram_sfi1.tdf" "" { Text "D:/baby/lab_dream/Liid/db/altsyncram_sfi1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "high VCC " "Warning (13410): Pin \"high\" is stuck at VCC" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 22 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 0}
{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Info: Found the following redundant logic cells in design" {  } {  } 0 0 "Found the following redundant logic cells in design" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "c:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "17 " "Warning: Design contains 17 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "cs1 " "Warning (15610): No output dependent on input pin \"cs1\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 11 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "cs4 " "Warning (15610): No output dependent on input pin \"cs4\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 13 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "cs5 " "Warning (15610): No output dependent on input pin \"cs5\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 14 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "oe " "Warning (15610): No output dependent on input pin \"oe\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 15 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "addr\[6\] " "Warning (15610): No output dependent on input pin \"addr\[6\]\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 18 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "addr\[7\] " "Warning (15610): No output dependent on input pin \"addr\[7\]\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 18 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "addr\[8\] " "Warning (15610): No output dependent on input pin \"addr\[8\]\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 18 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "addr\[9\] " "Warning (15610): No output dependent on input pin \"addr\[9\]\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 18 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "addr\[10\] " "Warning (15610): No output dependent on input pin \"addr\[10\]\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 18 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "addr\[11\] " "Warning (15610): No output dependent on input pin \"addr\[11\]\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 18 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "addr\[12\] " "Warning (15610): No output dependent on input pin \"addr\[12\]\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 18 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "addr\[13\] " "Warning (15610): No output dependent on input pin \"addr\[13\]\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 18 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "addr\[14\] " "Warning (15610): No output dependent on input pin \"addr\[14\]\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 18 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "addr\[15\] " "Warning (15610): No output dependent on input pin \"addr\[15\]\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 18 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "keys\[1\] " "Warning (15610): No output dependent on input pin \"keys\[1\]\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 20 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "keys\[2\] " "Warning (15610): No output dependent on input pin \"keys\[2\]\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 20 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "keys\[3\] " "Warning (15610): No output dependent on input pin \"keys\[3\]\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 20 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "1059 " "Info: Implemented 1059 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "39 " "Info: Implemented 39 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Info: Implemented 7 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "979 " "Info: Implemented 979 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_RAMS" "33 " "Info: Implemented 33 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 28 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 28 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "193 " "Info: Peak virtual memory: 193 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 23 22:15:42 2009 " "Info: Processing ended: Thu Apr 23 22:15:42 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:48 " "Info: Elapsed time: 00:00:48" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:28 " "Info: Total CPU time (on all processors): 00:00:28" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}