prev_cmp_liid.map.qmsg

利用fpga实现vga解码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 23 22:14:54 2009 " "Info: Processing started: Thu Apr 23 22:14:54 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off liid -c liid " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off liid -c liid" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "src/top.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file src/top.v" { { "Info" "ISGN_ENTITY_NAME" "1 liid " "Info: Found entity 1: liid" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "src/vga_ctr.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file src/vga_ctr.v" { { "Info" "ISGN_ENTITY_NAME" "1 vga " "Info: Found entity 1: vga" {  } { { "src/vga_ctr.v" "" { Text "D:/baby/lab_dream/Liid/src/vga_ctr.v" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "src/video_buffer.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file src/video_buffer.v" { { "Info" "ISGN_ENTITY_NAME" "1 video_buffer " "Info: Found entity 1: video_buffer" {  } { { "src/video_buffer.v" "" { Text "D:/baby/lab_dream/Liid/src/video_buffer.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "liid " "Info: Elaborating entity \"liid\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "key top.v(24) " "Warning (10858): Verilog HDL warning at top.v(24): object key used but never assigned" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 24 0 0 } }  } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "addr_from_key top.v(35) " "Warning (10036): Verilog HDL or VHDL warning at top.v(35): object \"addr_from_key\" assigned a value but never read" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 35 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "video_buffer video_buffer:video_bufferk " "Info: Elaborating entity \"video_buffer\" for hierarchy \"video_buffer:video_bufferk\"" {  } { { "src/top.v" "video_bufferk" { Text "D:/baby/lab_dream/Liid/src/top.v" 90 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "vga vga:vgak " "Info: Elaborating entity \"vga\" for hierarchy \"vga:vgak\"" {  } { { "src/top.v" "vgak" { Text "D:/baby/lab_dream/Liid/src/top.v" 99 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "xpos vga_ctr.v(38) " "Warning (10036): Verilog HDL or VHDL warning at vga_ctr.v(38): object \"xpos\" assigned a value but never read" {  } { { "src/vga_ctr.v" "" { Text "D:/baby/lab_dream/Liid/src/vga_ctr.v" 38 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "ypos vga_ctr.v(38) " "Warning (10036): Verilog HDL or VHDL warning at vga_ctr.v(38): object \"ypos\" assigned a value but never read" {  } { { "src/vga_ctr.v" "" { Text "D:/baby/lab_dream/Liid/src/vga_ctr.v" 38 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "addr_b video_bufferk 32 10 " "Warning (12020): Port \"addr_b\" on the entity instantiation of \"video_bufferk\" is connected to a signal of width 32. The formal width of the signal in the module is 10.  Extra bits will be ignored." {  } { { "src/top.v" "video_bufferk" { Text "D:/baby/lab_dream/Liid/src/top.v" 90 0 0 } }  } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be ignored." 0 0 "" 0 0}