prev_cmp_liid.qmsg

利用fpga实现vga解码

{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Info: Found the following redundant logic cells in design" {  } {  } 0 0 "Found the following redundant logic cells in design" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "c:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 113 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "17 " "Warning: Design contains 17 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "cs1 " "Warning (15610): No output dependent on input pin \"cs1\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 11 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "cs4 " "Warning (15610): No output dependent on input pin \"cs4\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 13 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "cs5 " "Warning (15610): No output dependent on input pin \"cs5\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 14 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "oe " "Warning (15610): No output dependent on input pin \"oe\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 15 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "addr\[6\] " "Warning (15610): No output dependent on input pin \"addr\[6\]\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 18 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "addr\[7\] " "Warning (15610): No output dependent on input pin \"addr\[7\]\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 18 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "addr\[8\] " "Warning (15610): No output dependent on input pin \"addr\[8\]\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 18 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "addr\[9\] " "Warning (15610): No output dependent on input pin \"addr\[9\]\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 18 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "addr\[10\] " "Warning (15610): No output dependent on input pin \"addr\[10\]\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 18 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "addr\[11\] " "Warning (15610): No output dependent on input pin \"addr\[11\]\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 18 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "addr\[12\] " "Warning (15610): No output dependent on input pin \"addr\[12\]\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 18 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "addr\[13\] " "Warning (15610): No output dependent on input pin \"addr\[13\]\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 18 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "addr\[14\] " "Warning (15610): No output dependent on input pin \"addr\[14\]\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 18 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "addr\[15\] " "Warning (15610): No output dependent on input pin \"addr\[15\]\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 18 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "keys\[1\] " "Warning (15610): No output dependent on input pin \"keys\[1\]\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 20 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "keys\[2\] " "Warning (15610): No output dependent on input pin \"keys\[2\]\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 20 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "keys\[3\] " "Warning (15610): No output dependent on input pin \"keys\[3\]\"" {  } { { "src/top.v" "" { Text "D:/baby/lab_dream/Liid/src/top.v" 20 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "1059 " "Info: Implemented 1059 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "39 " "Info: Implemented 39 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Info: Implemented 7 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "979 " "Info: Implemented 979 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_RAMS" "33 " "Info: Implemented 33 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 28 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 28 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "193 " "Info: Peak virtual memory: 193 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 23 22:15:42 2009 " "Info: Processing ended: Thu Apr 23 22:15:42 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:48 " "Info: Elapsed time: 00:00:48" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:28 " "Info: Total CPU time (on all processors): 00:00:28" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 23 22:15:47 2009 " "Info: Processing started: Thu Apr 23 22:15:47 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off liid -c liid " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off liid -c liid" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "liid EP2C8Q208C8 " "Info: Selected device EP2C8Q208C8 for design \"liid\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208C8 " "Info: Device EP2C5Q208C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C5Q208I8 " "Info: Device EP2C5Q208I8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8Q208I8 " "Info: Device EP2C8Q208I8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "2 " "Info: Fitter converted 2 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 0}