prev_cmp_liid.tan.qmsg

利用fpga实现vga解码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] register sld_hub:sld_hub_inst\|hub_tdo_reg 97.81 MHz 10.224 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 97.81 MHz between source register \"sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo_reg\" (period= 10.224 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.851 ns + Longest register register " "Info: + Longest register to register delay is 4.851 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\] 1 REG LCFF_X28_Y14_N3 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X28_Y14_N3; Fanout = 12; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:BROADCAST\|Q\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.505 ns) 0.956 ns sld_hub:sld_hub_inst\|node_ena~10 2 COMB LCCOMB_X28_Y14_N24 5 " "Info: 2: + IC(0.451 ns) + CELL(0.505 ns) = 0.956 ns; Loc. = LCCOMB_X28_Y14_N24; Fanout = 5; COMB Node = 'sld_hub:sld_hub_inst\|node_ena~10'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.956 ns" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] sld_hub:sld_hub_inst|node_ena~10 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" 136 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.702 ns) + CELL(0.206 ns) 1.864 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|crc_rom_sr_ena~32 3 COMB LCCOMB_X29_Y14_N26 5 " "Info: 3: + IC(0.702 ns) + CELL(0.206 ns) = 1.864 ns; Loc. = LCCOMB_X29_Y14_N26; Fanout = 5; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|crc_rom_sr_ena~32'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.908 ns" { sld_hub:sld_hub_inst|node_ena~10 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~32 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" 806 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.390 ns) + CELL(0.206 ns) 2.460 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|status_shift_enable~58 4 COMB LCCOMB_X29_Y14_N12 18 " "Info: 4: + IC(0.390 ns) + CELL(0.206 ns) = 2.460 ns; Loc. = LCCOMB_X29_Y14_N12; Fanout = 18; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|status_shift_enable~58'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.596 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~32 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~58 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" 834 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.368 ns) + CELL(0.206 ns) 3.034 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~442 5 COMB LCCOMB_X29_Y14_N6 1 " "Info: 5: + IC(0.368 ns) + CELL(0.206 ns) = 3.034 ns; Loc. = LCCOMB_X29_Y14_N6; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~442'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.574 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status_shift_enable~58 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~442 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" 518 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.362 ns) + CELL(0.206 ns) 3.602 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~445 6 COMB LCCOMB_X29_Y14_N28 1 " "Info: 6: + IC(0.362 ns) + CELL(0.206 ns) = 3.602 ns; Loc. = LCCOMB_X29_Y14_N28; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|tdo~445'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.568 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~442 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~445 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_signaltap.vhd" 518 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.377 ns) + CELL(0.206 ns) 4.185 ns sld_hub:sld_hub_inst\|hub_tdo_reg~294 7 COMB LCCOMB_X29_Y14_N0 1 " "Info: 7: + IC(0.377 ns) + CELL(0.206 ns) = 4.185 ns; Loc. = LCCOMB_X29_Y14_N0; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~294'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.583 ns" { sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|tdo~445 sld_hub:sld_hub_inst|hub_tdo_reg~294 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.352 ns) + CELL(0.206 ns) 4.743 ns sld_hub:sld_hub_inst\|hub_tdo_reg~295 8 COMB LCCOMB_X29_Y14_N4 1 " "Info: 8: + IC(0.352 ns) + CELL(0.206 ns) = 4.743 ns; Loc. = LCCOMB_X29_Y14_N4; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~295'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.558 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~294 sld_hub:sld_hub_inst|hub_tdo_reg~295 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 4.851 ns sld_hub:sld_hub_inst\|hub_tdo_reg 9 REG LCFF_X29_Y14_N5 2 " "Info: 9: + IC(0.000 ns) + CELL(0.108 ns) = 4.851 ns; Loc. = LCFF_X29_Y14_N5; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~295 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/80/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.849 ns ( 38.12 % ) " "Info: Total cell delay = 1.849 ns ( 38.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.002 ns ( 61.88 % ) " "Info: Total interconnect delay = 3.002 ns ( 61.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.851 ns" { sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] sld_hub:sld_hub_inst|node_ena~10 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|crc_rom_sr_ena~32 sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|status