decode_jra.tdf

利用fpga实现vga解码

--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_DECODES=193 LPM_WIDTH=8 data enable eq
--VERSION_BEGIN 8.0 cbx_cycloneii 2008:02:23:252825 cbx_lpm_add_sub 2008:03:09:257947 cbx_lpm_compare 2008:02:23:252825 cbx_lpm_decode 2008:02:23:252825 cbx_mgl 2008:04:11:273944 cbx_stratix 2008:02:23:252825 cbx_stratixii 2008:02:23:252825  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
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--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 292 
SUBDESIGN decode_jra
( 
	data[7..0]	:	input;
	enable	:	input;
	eq[192..0]	:	output;
) 
VARIABLE 
	data_wire[7..0]	: WIRE;
	enable_wire	: WIRE;
	eq_node[192..0]	: WIRE;
	eq_wire[255..0]	: WIRE;
	w_anode12756w[2..0]	: WIRE;
	w_anode12771w[3..0]	: WIRE;
	w_anode12788w[3..0]	: WIRE;
	w_anode12805w[3..0]	: WIRE;
	w_anode12815w[3..0]	: WIRE;
	w_anode12825w[3..0]	: WIRE;
	w_anode12835w[3..0]	: WIRE;
	w_anode12845w[3..0]	: WIRE;
	w_anode12855w[3..0]	: WIRE;
	w_anode12865w[3..0]	: WIRE;
	w_anode12877w[3..0]	: WIRE;
	w_anode12888w[3..0]	: WIRE;
	w_anode12899w[3..0]	: WIRE;
	w_anode12909w[3..0]	: WIRE;
	w_anode12919w[3..0]	: WIRE;
	w_anode12929w[3..0]	: WIRE;
	w_anode12939w[3..0]	: WIRE;
	w_anode12949w[3..0]	: WIRE;
	w_anode12959w[3..0]	: WIRE;
	w_anode12970w[3..0]	: WIRE;
	w_anode12981w[3..0]	: WIRE;
	w_anode12992w[3..0]	: WIRE;
	w_anode13002w[3..0]	: WIRE;
	w_anode13012w[3..0]	: WIRE;
	w_anode13022w[3..0]	: WIRE;
	w_anode13032w[3..0]	: WIRE;
	w_anode13042w[3..0]	: WIRE;
	w_anode13052w[3..0]	: WIRE;
	w_anode13063w[3..0]	: WIRE;
	w_anode13074w[3..0]	: WIRE;
	w_anode13085w[3..0]	: WIRE;
	w_anode13095w[3..0]	: WIRE;
	w_anode13105w[3..0]	: WIRE;
	w_anode13115w[3..0]	: WIRE;
	w_anode13125w[3..0]	: WIRE;
	w_anode13135w[3..0]	: WIRE;
	w_anode13145w[3..0]	: WIRE;
	w_anode13156w[3..0]	: WIRE;
	w_anode13167w[3..0]	: WIRE;
	w_anode13178w[3..0]	: WIRE;
	w_anode13188w[3..0]	: WIRE;
	w_anode13198w[3..0]	: WIRE;
	w_anode13208w[3..0]	: WIRE;
	w_anode13218w[3..0]	: WIRE;
	w_anode13228w[3..0]	: WIRE;
	w_anode13238w[3..0]	: WIRE;
	w_anode13249w[3..0]	: WIRE;
	w_anode13260w[3..0]	: WIRE;
	w_anode13271w[3..0]	: WIRE;
	w_anode13281w[3..0]	: WIRE;
	w_anode13291w[3..0]	: WIRE;
	w_anode13301w[3..0]	: WIRE;
	w_anode13311w[3..0]	: WIRE;
	w_anode13321w[3..0]	: WIRE;
	w_anode13331w[3..0]	: WIRE;
	w_anode13342w[3..0]	: WIRE;
	w_anode13353w[3..0]	: WIRE;
	w_anode13364w[3..0]	: WIRE;
	w_anode13374w[3..0]	: WIRE;
	w_anode13384w[3..0]	: WIRE;
	w_anode13394w[3..0]	: WIRE;
	w_anode13404w[3..0]	: WIRE;
	w_anode13414w[3..0]	: WIRE;
	w_anode13424w[3..0]	: WIRE;
	w_anode13435w[3..0]	: WIRE;
	w_anode13446w[3..0]	: WIRE;
	w_anode13457w[3..0]	: WIRE;
	w_anode13467w[3..0]	: WIRE;
	w_anode13477w[3..0]	: WIRE;
	w_anode13487w[3..0]	: WIRE;
	w_anode13497w[3..0]	: WIRE;
	w_anode13507w[3..0]	: WIRE;
	w_anode13517w[3..0]	: WIRE;
	w_anode13530w[2..0]	: WIRE;
	w_anode13540w[3..0]	: WIRE;
	w_anode13551w[3..0]	: WIRE;
	w_anode13568w[3..0]	: WIRE;
	w_anode13578w[3..0]	: WIRE;
	w_anode13588w[3..0]	: WIRE;
	w_anode13598w[3..0]	: WIRE;
	w_anode13608w[3..0]	: WIRE;
	w_anode13618w[3..0]	: WIRE;
	w_anode13628w[3..0]	: WIRE;
	w_anode13640w[3..0]	: WIRE;
	w_anode13651w[3..0]	: WIRE;
	w_anode13662w[3..0]	: WIRE;
	w_anode13672w[3..0]	: WIRE;
	w_anode13682w[3..0]	: WIRE;
	w_anode13692w[3..0]	: WIRE;
	w_anode13702w[3..0]	: WIRE;