top.v

利用fpga实现vga解码

module liid(
	input clk,
	input rst_n,
	
	output hsync,//行同步信号
	output vsync,//场同步信号
	output vga_r,
	output vga_g,
	output vga_b,

	input cs1,
	input cs2,
	input cs4,
	input cs5,
	input oe,
	input we,
	input [7:0]data,
	input [15:0]addr,
	
	input [3:0]keys,
	output high
		);

reg [3:0]key; 
reg [31:0]rgb_data;
reg [31:0]addr_b_from_key;
reg [31:0]addr_b_inc;
wire rgb_to_ctr;

wire we_a_from_arm;
assign we_a_from_arm = ~(we | cs2);
assign high = 1;


reg [15:0]addr_b;
reg [9:0]addr_from_key;
reg [9:0]addr_from_arm;
reg [15:0]addr_a;
wire [7:0]q_b;

reg [7:0]data_from_key;
reg [7:0]data_from_arm;

always @(posedge clk)begin
	data_from_arm <= data;
	addr_from_arm <= addr[5:0];
end

always @(posedge clk)begin
	addr_from_key <= {key,4'b1111};
end

/*
always @(posedge clk)begin
	key <= keys;
	
	if(addr_b > 1024*768)
		addr_b <= 0;
	else	
		addr_b <= addr_b + 1;
	
	if(addr_a > 860*5)
		addr_a <= 0;
	else	
		addr_a <= addr_a + 1;	
		
	data_from_key <= {keys, 4'b1111};
	if(rgb_to_ctr)
		addr_b_r <= addr_b_r + 1;
	else
		addr_b_r <= 0;
end
*/


always @(posedge keys[0])begin
	if(addr_b_from_key > 16)begin
		addr_b_from_key <= 0;
	end else begin
		addr_b_from_key <= addr_b_from_key + 1;
	end
end

always @(posedge clk)begin
	if(addr_b_inc > 16)begin
		addr_b_inc <= 0;
	end else begin
		addr_b_inc <= addr_b_inc + 1;
	end
end


//assign we_a = ~keys[0];
video_buffer video_bufferk(
	.clk(clk), 
	.we_a(we_a_from_arm), .data_a(data_from_arm), .addr_a(addr_from_arm), /*.q_a(),*/
	.we_b(~high), /*.data_b(), */.addr_b(addr_b_inc), .q_b(q_b)
);

vga vgak(
		.clk(clk), .rst_n(rst_n), 
		.hsync(hsync), .vsync(vsync), 
		.vga_r(vga_r), .vga_g(vga_g), .vga_b(vga_b), 
		//.RGB(data[5:3]), 
		.RGB(q_b[2:0]), 
		.Rgb_valid(rgb_to_ctr)
);

endmodule