video_buffer.v

来自「利用fpga实现vga解码」· Verilog 代码 · 共 45 行

module video_buffer
(
	input [(8-1):0] data_a, 
	input [(8-1):0] data_b,
	input [(10-1):0] addr_a, 
	input [(10-1):0] addr_b,
	input we_a, 
	input we_b, 
	input clk,
	
	output reg [(8-1):0] q_a, 
	output reg [(8-1):0] q_b
);

	parameter DATA_WIDTH = 8;
	parameter ADDR_WIDTH = 10;

	// Declare the RAM variable
	//reg [DATA_WIDTH-1:0] ram[1024*768:0];
	reg [DATA_WIDTH-1:0] ram[128:0];

	// Port A 
	always @ (posedge clk)	begin
		if (we_a) begin
			ram[addr_a] <= data_a;
			q_a <= data_a;
		end	else	begin
			q_a <= ram[addr_a];
		end 
	end 

	// Port B 
	always @ (posedge clk)	begin 
		if (we_b) begin
				//ram[addr_b] <= data_b;
			q_b <= q_b;
		end	else	begin
			q_b <= ram[addr_b];
		end 
	end

endmodule