liid.map.rpt

利用fpga实现vga解码

Analysis & Synthesis report for liid
Thu Apr 23 22:20:36 2009
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. Registers Removed During Synthesis
  9. General Register Statistics
 10. Inverted Register Statistics
 11. Registers Added for RAM Pass-Through Logic
 12. Multiplexer Restructuring Statistics (Restructuring Performed)
 13. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body
 14. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst
 15. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_15p3:auto_generated
 16. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:\adv_point_3_and_more:advance_pointer_counter
 17. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:read_pointer_counter
 18. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:status_advance_pointer_counter
 19. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:status_read_pointer_counter
 20. Source assignments for sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr
 21. Source assignments for sld_hub:sld_hub_inst
 22. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
 23. Source assignments for video_buffer:video_bufferk|altsyncram:ram__dual_rtl_0|altsyncram_jpi1:auto_generated
 24. Parameter Settings for User Entity Instance: video_buffer:video_bufferk
 25. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
 26. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 27. Parameter Settings for Inferred Entity Instance: video_buffer:video_bufferk|altsyncram:ram__dual_rtl_0
 28. SignalTap II Logic Analyzer Settings
 29. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Thu Apr 23 22:20:35 2009    ;
; Quartus II Version                 ; 8.0 Build 215 05/29/2008 SJ Full Version ;
; Revision Name                      ; liid                                     ;