vlog_ref_body.html

verilog语法手册速查,能帮组快速的学习Verilog

<div align="center"><center>

<table border="1" cellspacing="1" cellpadding="4" width="625" BGcolor="#E0E0E0">
  <tr>
    <td width="40%"><p align="center"><b>Data Type Examples</b></td>
    <td width="50%"><p align="center"><b>Notes</b></td>
  </tr>
  <tr>
    <td width="40%"><font color="#00AA00"><code>wire a, b, c;</code></font></td>
    <td width="50%">3 scalar nets</td>
  </tr>
  <tr>
    <td width="40%"><font color="#00AA00"><code>tri1 [7:0] data_bus;</code></font></td>
    <td width="50%">8-bit net, pulls-up when tri-stated</td>
  </tr>
  <tr>
    <td width="40%"><font color="#00AA00"><code>reg [1:8] result;</code></font></td>
    <td width="50%">an 8-bit unsigned variable</td>
  </tr>
  <tr>
    <td width="40%"><font color="#00AA00"><code>reg [7:0] RAM [0:1023];</code></font></td>
    <td width="50%">a memory array; 8-bits wide, with 1K of addresses</td>
  </tr>
  <tr>
    <td width="40%"><font color="#00AA00"><code>wire #(2.4,1.8) carry;</code></font></td>
    <td width="50%">a net with rise, fall delays</td>
  </tr>
  <tr>
    <td width="40%"><font color="#00AA00"><code>wire (strong1,pull0) sum = a+b;</code></font></td>
    <td width="50%">net with drive strength and a continuous assignment</td>
  </tr>
  <tr>
    <td width="40%"><font color="#00AA00"><code>trireg (small) #(0,0,35) ram_bit;</code></font></td>
    <td width="50%">net with small capacitance and 35 time unit decay time</td>
  </tr>
</table>
</center></div>

<p>&nbsp;</p>

<hr>

<h3><a name="8.0 Module Instances"><font color="#0000FF">8.0 Module Instances</font></a></h3>
<div align="center"><center>

<table border="1" cellspacing="1" cellpadding="4" width="712" BGcolor="#FFFFFF">
  <tr>
    <td width="700"><p align="center"><b>Syntax</b></td>
  </tr>
  <tr>
    <td width="700"><p align="center"><b>Port Order Connections</b></p>
    <p><font color="#00AA00"><i>module_name</i></font> <a href="#mod_instance_name">instance_name</a>
    <font color="#FF0000"><code>[</code></font><a href="#mod_instance_array_range">instance_array_range</a><font color="#FF0000"><code>]</code></font> <font color="#FF0000"><code>(</code></font><font color="#00AA00"><i>signal</i></font><font color="#FF0000"><code>,</code></font> <font color="#00AA00"><i>signal</i></font><font color="#FF0000"><code>,</code></font> <font color="#00AA00">... </font><font color="#FF0000"><code>);</code></font></td>
  </tr>
  <tr>
    <td width="700"><p align="center"><b>Port Name Connections</b></p>
    <p><font color="#00AA00"><i>module_name</i></font> <a href="#mod_instance_name">instance_name</a>
    <font color="#FF0000"><code>[</code></font><a href="#mod_instance_array_range">instance_array_range</a><font color="#FF0000"><code>]</code></font> <font color="#FF0000"><code>(.</code></font><font color="#00AA00"><i>port_name</i></font><font color="#FF0000"><code>(</code></font><font color="#00AA00"><i>signal</i></font><font color="#FF0000"><code>),</code></font> <font color="#FF0000"><code>(.</code></font><font color="#00AA00"><i>port_name</i></font><font color="#FF0000"><code>(</code></font><font color="#00AA00"><i>signal</i></font><font color="#FF0000"><code>),</code></font> <font color="#00AA00">...</font><font color="#FF0000"><code>);</code></font></td>
  </tr>
  <tr>
    <td width="700"><p align="center"><b>Explicit Parameter Redefinition</b></p>
    <p><font color="#FF0000"><code>defparam</code></font> <font color="#00AA00"><i>heirarchy_path</i></font><font color="#FF0000"><code>.</code></font><font color="#00AA00"><i>parameter_name</i></font> <font color="#FF0000"><code>=</code></font> <font color="#00AA00"><i>value</i></font><font color="#FF0000"><code>;</code></font></td>
  </tr>
  <tr>
    <td width="700"><p align="center"><b>Implicit Parameter Redefinition</b></p>
    <p><font color="#00AA00"><i>module_name</i></font> <font color="#FF0000"><code>#(</code></font><font color="#00AA00"><i>value</i></font><font color="#FF0000"><code>)</code></font> <font color="#00AA00"><i>instance_name</i></font> <font color="#FF0000"><code>(</code></font><font color="#00AA00"><i>signals</i></font><font color="#FF0000"><code>);</code></font></td>
  </tr>
</table>
</center></div>

<p>&nbsp;</p>

<p>A module may be instantiated using port order or port names.<br>

<ul type="disc">
  <li>Port order instantiation lists signal connections in the same order as the port list in
    the module definition. Unconnected ports are designated by two commas with no signal
    listed.</li>
  <li>Port name instantiation lists the port name and signal connected to it, in any order.</li>
</ul>

<p><a name="mod_instance_name"><font color="#0000FF"><i>instance_name</i></font></a>
(required) is used to make multiple instances of the same module unique from one another.</p>

<p><a name="mod_instance_array_range"><font color="#0000FF"><i>instance_array_range</i></font></a>
(optional) instantiates multiple modules, each instance connected to separate bits of a
vector.<br>

<ul type="disc">
  <li>The range is specified as <font color="#FF0000"><code>[</code></font><font color="#00AA00"><i>lhi</i></font><font color="#FF0000"><code>:</code></font><font color="#00AA00"><i>rhi</i></font><font color="#FF0000"><code>]</code></font>
    (left-hand-index to right-hand-index).</li>
  <li>If the bit width of a module port in the array is the same as the width of the signal
    connected to it, the full signal is connected to each instance of the module port.</li>
  <li>If the bit width of a module port is different than the width of the signal connected to
    it, each module port instance is connected to a part select of the signal, with the
    right-most instance index connected to the right-most part of the vector, and progressing
    towards the left.</li>
  <li>There must be the correct number of bits in each signal to connect to all instances (the
    signal size and port size must be multiples).</li>
</ul>

<p>Parameters in a module may be redefined for each instance.<br>

<ul type="disc">
  <li>Explicit redefinition uses a <code><font color="#FF0000">defparam</font></code>
    statement with the parameter's hierarchical name.</li>
  <li>Implicit redefinition uses the <code><font color="#FF0000">#</font></code> token as part
    of the module instantiation. Parameters must be redefined in the same order they are
    declared within the module.</li>
</ul>

<p>&nbsp;</p>
<div align="center"><center>

<table border="1" cellspacing="1" cellpadding="4" width="500" BGcolor="#E0E0E0">
  <tr>
    <td><p align="center"><b>Module Instance Examples</b></td>
  </tr>
  <tr>
    <td><code><pre>
module reg4 (q, d, clock);
  output [3:0] q;
  input [3:0] d;
  input clock;
  wire [3:0] q, d;
  wire clock;
  <font color="#00AA00"><b>
  //port order connection,2nd port not connected
  dff u1 (q[0], , d[0], clock);

  //port name connection, qb not connected
  dff u2 (.clk(clock),.q(q[1]),.data(d[1]));

  //explicit parameter redefine
  dff u3 (q[2], ,d[2], clock);
  defparam u3.delay = 3.2;

  //implicit parameter redefine
  dff #(2) u4 (q[3], , d[3], clock);</b></font>
endmodule</code></pre>
    </td>
  </tr>
  <tr>
    <td><code><pre>
module dff (q, qb, data, clk);
  output q, qb;
  input data, clk;

  parameter delay = 1; //default delay parameter

  dff_udp #(delay) (q, data, clk);
  not (qb, q);
endmodule</code></pre>
    </td>
  </tr>
</table>
</center></div>

<p>&nbsp;</p>
<div align="center"><center>

<table border="1" cellspacing="1" cellpadding="4" width="500" BGcolor="#E0E0E0">
  <tr>
    <td><p align="center"><b>Array of Instances Example</b></td>
  </tr>
  <tr>
    <td><code><pre>
module tribuf64bit (out, in, enable);
  output [63:0] out;
  input [63:0] in;
  input enable;
  wire [63:0] out, in;
  wire enable;
  <font color="#00AA00"><b>
  //array of 8 8-bit tri-state buffers; each instance is connected
  //to 8-bit part selects of the 64-bit vectors; The scalar
  //enable line is connected to all instances

  tribuf8bit i[7:0] (out, in, enable);</b></font>

endmodule</code></pre>
    </td>
  </tr>
  <tr>
    <td><code><pre>
module tribuf8bit (out, in, enable);
  output [7:0] y;
  input [7:0] a;
  input en;
  wire [7:0] y, a;
  wire en;
  <font color="#00AA00"><b>
  //array of 8 Verilog tri-state primitives each bit of the
  //vectors is connected to a different primitive instance
  bufif1 u[7:0] (y, a, en);</b></font>
endmodule</code></pre>
    </td>
  </tr>
</table>
</center></div>

<p>&nbsp;</p>

<hr>

<h3><a name="9.0 Primitive Instances"><font color="#0000FF">9.0 Primitive Instances</font></a></h3>
<div align="center"><center>

<table border="1" cellspacing="1" cellpadding="4" width="700" BGcolor="#FFFFFF">
  <tr>
    <td><p align="center"><b>Syntax</b></td>
  </tr>
  <tr>
    <td><a href="#Gate Type">gate_type</a> <font color="#FF0000"><code>(</code></font><font color="#00AA00"><i>drive_strength</i></font><font color="#FF0000"><code>)</code></font> <font color="#FF0000"><code>#(</code></font><font color="#00AA00"><i>delay</i></font><font color="#FF0000"><code>)</code></font> <a href="#prim_instance_name">instance_name</a> <font color="#FF0000"><code>[</code></font><a href="#prim_instance_array_range">instance_array_range</a><font color="#FF0000"><code>]</code></font> <font color="#FF0000"><code>(</code></font><font color="#00AA00"><i>terminal</i></font><font color="#FF0000"><code>,</code></font> <font color="#00AA00"><i>terminal</i></font><font color="#FF0000"><code>,</code></font> <font color="#00AA00">... <font color="#FF0000"><code>);</code></font></font></td>
  </tr>
  <tr>
    <td><a href="#Switch Type">switch_type</a> <font color="#FF0000"><code>#(</code></font><font color="#00AA00"><i>delay</i></font><font color="#FF0000"><code>)</code></font> <a href="#prim_instance_name">instance_name</a> <font color="#FF0000"><code>[</code></font><a href="#prim_instance_array_range">instance_array_range</a><font color="#FF0000"><code>]</code></font>
    <font color="#FF0000"><code>(</code></font><font color="#00AA00"><i>terminal</i></font><font color="#FF0000"><code>,</code></font> <font color="#00AA00"><i>terminal</i></font><font color="#FF0000"><code>,</code></font> <font color="#00AA00">... <font color="#FF0000"><code>);</code></font></font></td>
  </tr>
</table>
</center></div>

<p>&nbsp;</p>
<div align="center"><center>

<table border="1" cellspacing="1" cellpadding="4" width="502" BGcolor="#FFFFFF">
  <tr>
    <td width="170" COLSPAN="2"><b><p align="center"><a name="Gate Type">Gate Type</a></b></td>
    <td width="306"><b><p align="center">Terminal Order</b></td>
  </tr>
  <tr>
    <td width="78"><font color="#FF0000"><code>and<br>
    or<br>
    xor</code></font></td>
    <td width="82"><font color="#FF0000"><code>nand<br>
    nor<br>
    </code>xnor</font></td>
    <td width="306">(1_output, 1-or-more_inputs)</td>
  </tr>
  <tr>
    <td width="78"><font color="#FF0000"><code>buf</code></font></td>
    <td width="82"><font color="#FF0000"><code>not</code></font></td>
    <td width="306">(1-or-more_outputs, 1_input)</td>
  </tr>
  <tr>
    <td width="78"><font color="#FF0000"><code>bufif0<br>
    bufif1</code></font></td>
    <td width="82"><font color="#FF0000"><code>notif0<br>
    notif1</code></font></td>
    <td width="306">(1_output, 1_input, 1_control)</td>
  </tr>
  <tr>
    <td width="78"><font color="#FF0000"><code>pullup</code></font></td>
    <td width="82"><font color="#FF0000"><code>pulldown</code></font></td>
    <td width="306">(1_output)</td>
  </tr>
  <tr>
    <td width="170" COLSPAN="2"><a href="#16.0 User Defined Primitives (UDPs)">user-defined-primitives</a></td>
    <td width="306">(1_output, 1-or-more_inputs)</td>
  </tr>
</table>
</center></div>

<p>&nbsp;</p>
<div align="center"><center>

<table border="1" cellspacing="1" cellpadding="4" width="500" BGcolor="#FFFFFF">
  <tr>
    <td width="24%" COLSPAN="2"><b><p align="center"><a name="Switch Type">Switch Type</a></b></td>
    <td width="76%"><b><p align="center">Terminal Order</b></td>
  </tr>
  <tr>
    <td width="12%"><font color="#FF0000"><code>pmos<br>
    nmos</code></font></td>
    <td width="12%"><font color="#FF0000"><code>rpmos<br>
    rnmos</code></font></td>