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<p align="center"><font size=+2 color="#0000FF"><b><i>On-line Verilog HDL Quick Reference
Guide</i></b></font><br>
by Stuart Sutherland of Sutherland HDL, Inc. - Portland, Oregon, USA</p>
<p align="center"><font size=-1 color="#FF0000">copyrighted material - do not reproduce
any portion by any means</font><br>
<font size=-1 color="#0000FF">professionally printed reference guides are available - see
www.sutherland.com for details</font></p>
<hr>
<h3><a name="1.0 Hierarchy Scopes"><font color="#0000FF">1.0 Hierarchy Scopes</font></a></h3>
<p>Verilog HDL constructs that represent hierarchy scope are:<br>
<ul type="disc">
<li><a href="#5.0 Module Definitions">Module definitions</a></li>
<li><a href="#13.0 Task Definitions">Function definitions</a> </li>
<li><a href="#13.0 Task Definitions">Task definitions</a> </li>
<li><a href="#10.0 Procedural Blocks">Named statement blocks</a> ( <code><font color="#FF0000">begin</font></code>- <code><font color="#FF0000">end</font></code> or <code><font color="#FF0000">fork</font></code>- <code><font color="#FF0000">join</font></code>) </li>
<li><a href="#15.0 Specify Blocks">Specify blocks</a> </li>
</ul>
<p>Each scope has its own name space. An identifier name defined within a scope is unique
to that scope. References to an identifier name will search first in the local scope, and
then search upward through the scope hierarchy up to a module boundary.</p>
<hr>
<h3><a name="2.0 Concurrency"><font color="#0000FF">2.0 Concurrency</font></a></h3>
<p>The following Verilog HDL constructs are independent processes that are evaluated
concurrently in simulation time:<br>
<ul type="disc">
<li><a href="#8.0 Module Instances">Module instances</a> </li>
<li><a href="#9.0 Primitive Instances">Primitive instances</a> </li>
<li><a href="#12.0 Continuous Assignments">Continuous assignments</a> </li>
<li><a href="#10.0 Procedural Blocks">Procedural blocks</a> </li>
</ul>
<hr>
<h3><a name="3.0 Reserved Keywords"><font color="#0000FF">3.0 Reserved Keywords</font></a></h3>
<div align="center"><center>
<table border="1" cellspacing="1" cellpadding="4" width="600" BGcolor="#FFFFFF">
<tr>
<td width="20%"><samp><font color="#FF0000">always<br>
and<br>
assign<br>
attribute<br>
begin<br>
buf<br>
bufif0<br>
bufif1<br>
case<br>
casex<br>
casez<br>
cmos<br>
deassign<br>
default<br>
defparam<br>
disable<br>
edge<br>
else<br>
end<br>
endattribute<br>
endcase<br>
endfunction </font></samp></td>
<td width="20%"><samp><font color="#FF0000">endmodule<br>
endprimitive<br>
endspecify<br>
endtable<br>
endtask<br>
event<br>
for<br>
force<br>
forever<br>
fork<br>
function<br>
highz0<br>
highz1<br>
if<br>
ifnone<br>
initial<br>
inout<br>
input<br>
integer<br>
join<br>
medium<br>
module </font></samp></td>
<td width="20%"><samp><font color="#FF0000">large<br>
macromodule<br>
nand<br>
negedge<br>
nmos<br>
nor<br>
not<br>
notif0<br>
notif1<br>
or<br>
output<br>
parameter<br>
pmos<br>
posedge<br>
primitive<br>
pull0<br>
pull1<br>
pulldown<br>
pullup<br>
rcmos<br>
real<br>
realtime </font></samp></td>
<td width="20%"><samp><font color="#FF0000">reg<br>
release<br>
repeat<br>
rnmos<br>
rpmos<br>
rtran<br>
rtranif0<br>
rtranif1<br>
scalared<br>
signed<br>
small<br>
specify<br>
specparam<br>
strength<br>
strong0<br>
strong1<br>
supply0<br>
supply1<br>
table<br>
task<br>
time<br>
tran </font></samp></td>
<td width="20%"><samp><font color="#FF0000">tranif0<br>
tranif1<br>
tri<br>
tri0<br>
tri1<br>
triand<br>
trior<br>
trireg<br>
unsigned<br>
vectored<br>
wait<br>
wand<br>
weak0<br>
weak1<br>
while<br>
wire<br>
wor<br>
xnor<br>
xor </font></samp></td>
</tr>
</table>
</center></div>
<p> </p>
<hr>
<h3><a name="4.0 Lexical Conventions"><font color="#0000FF">4.0 Lexical Conventions</font></a></h3>
<h4><a name="4.1 White Space Characters"><font color="#0000FF">4.1 White Space Characters</font></a></h4>
<i>
<p>blanks</i>, <i>tabs</i>, <i>newlines</i> (carriage return), <i>formfeeds</i> and <i>EOF
(end-of-file)</i>.</p>
<h4><a name="4.2 Comments"><font color="#0000FF">4.2 Comments</font></a></h4>
<p><code><font color="#FF0000">//</font> </code>begins a single line comment, terminated
by a newline.</p>
<p><code><font color="#FF0000">/*</font> </code>begins a multi-line comment, terminated by
a<code> <font color="#FF0000">*/</font></code>.</p>
<h4><a name="4.3 Case Sensitivity"><font color="#0000FF">4.3 Case Sensitivity</font></a></h4>
<p>Verilog is case sensitive.</p>
<h4><a name="4.4 Identifiers (names)"><font color="#0000FF">4.4 Identifiers (names)</font></a></h4>
<ul type="disc">
<li>Must begin with alphabetic or underscore characters <font color="#FF0000"><code>a</code></font>-<font color="#FF0000"><code>z A</code></font>-<code><font color="#FF0000">Z _</font></code></li>
<li>May contain the characters <font color="#FF0000"><code>a</code></font>-<font color="#FF0000"><code>z A</code></font>-<code><font color="#FF0000">Z 0</font></code>-<code><font color="#FF0000">9 _</font></code> and <code><font color="#FF0000">$</font></code></li>
<li>May use any character by escaping with a backslash (<font color="#FF0000"><code> \ </code></font>)
at the beginning of the identifier, and terminating with a white space.</li>
</ul>
<div align="center"><center>
<table border="1" cellspacing="1" cellpadding="4" width="538" BGcolor="#E0E0E0">
<tr>
<td width="30%"><p align="center"><b>Examples</b></td>
<td width="70%"><p align="center"><b>Notes</b></td>
</tr>
<tr>
<td width="30%"><p align="center"><code><font color="#00AA00">adder </font></code></td>
<td width="70%">legal identifier name</td>
</tr>
<tr>
<td width="30%"><p align="center"><code><font color="#00AA00">XOR </font></code></td>
<td width="70%">uppercase identifier is unique from xor keyword</td>
</tr>
<tr>
<td width="30%"><p align="center"><code><font color="#00AA00">\reset* </font></code></td>
<td width="70%">an escaped identifier (must be followed by a white space)</td>
</tr>
</table>
</center></div>
<p> </p>
<h4><a name="4.5 Logic Values"><font color="#0000FF">4.5 Logic Values</font></a></h4>
<p>The Verilog HDL has 4 logic values.</p>
<div align="center"><center>
<table border="1" cellspacing="1" cellpadding="4" width="472" BGcolor="#FFFFFF">
<tr>
<td width="34%"><p align="center"><b>Logic Value</b></td>
<td width="66%"><p align="center"><b>Description</b></td>
</tr>
<tr>
<td width="34%"><p align="center"><code><font color="#FF0000">0</font></code></td>
<td width="66%">zero, low, or false</td>
</tr>
<tr>
<td width="34%"><p align="center"><code><font color="#FF0000">1</font></code></td>
<td width="66%">one, high, or true</td>
</tr>
<tr>
<td width="34%"><p align="center"><code><font color="#FF0000">z</font></code> or <code><font color="#FF0000">Z</font></code></td>
<td width="66%">high impedance (tri-stated or floating)</td>
</tr>
<tr>
<td width="34%"><p align="center"><code><font color="#FF0000">x</font></code> or <code><font color="#FF0000">X</font></code></td>
<td width="66%">unknown or uninitialized</td>
</tr>
</table>
</center></div>
<p> </p>
<h4><a name="4.6 Logic Strengths"><font color="#0000FF">4.6 Logic Strengths</font></a></h4>
<p>The Verilog HDL has 8 logic strengths: 4 driving, 3 capacitive, and high impedance (no
strength).</p>
<div align="center"><center>
<table border="1" cellspacing="1" cellpadding="4" width="472" BGcolor="#FFFFFF">
<tr>
<td width="20%"><p align="center"><b>Strength Level</b></td>
<td width="31%"><p align="center"><b>Strength Name</b></td>
<td width="28%" COLSPAN="2"><p align="center"><b>Specification Keyword</b></td>
<td width="22%" COLSPAN="2"><p align="center"><b>Display Mnemonic</b></td>
</tr>
<tr>
<td width="20%"><p align="center">7</td>
<td width="31%">Supply Drive</td>
<td width="14%"><p align="center"><code><font color="#FF0000">supply0</font></code></td>
<td width="14%"><p align="center"><code><font color="#FF0000">supply1</font></code></td>
<td width="11%"><p align="center"><code><font color="#FF0000">Su0</font></code></td>
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